Abstract: Disclosed are a display panel and a display apparatus, the display panel includes a display region, the display region includes a light transmitting display region and a conventional display region located on at least one side of the light transmitting display region, the conventional display region includes a first region, a second region, and a third region; at least one circuit unit of the first region in the conventional display region is connected with a light emitting device in the light transmitting display region, at least one circuit unit of the third region in the conventional display region includes a data connection line, a second high-voltage power supply line includes a first sub-high-voltage power supply line and a second sub-high-voltage power supply line connected with each other, the second sub-high-voltage power supply line is located on a side of the first sub-high-voltage power supply line away from the base substrate.

Abstract: A display substrate and a display apparatus. The display substrate includes multiple circuit units, a circuit unit at least includes a pixel drive circuit, the pixel drive circuit at least includes a second transistor, a third transistor, a fourth transistor and a ninth transistor, a gate electrode of the third transistor is connected to a second electrode of the ninth transistor, a first electrode of the third transistor is connected to a second electrode of the fourth transistor, a second electrode of the third transistor is connected to a second electrode of the second transistor, and a first electrode of the second transistor is connected to a first electrode of the ninth transistor; the second transistor and the ninth transistor are configured such that a moment when the ninth transistor is turned off is earlier than a moment when the second transistor is turned off in the data writing stage.

Abstract: Disclosed are a display panel and a display apparatus, the display panel includes a display region, the display region includes a light transmitting display region and a conventional display region located on at least one side of the light transmitting display region, the conventional display region includes a first region, a second region, and a third region; at least one circuit unit of the first region in the conventional display region is connected with a light emitting device in the light transmitting display region, at least one circuit unit of the third region in the conventional display region includes a data connection line, a second high-voltage power supply line includes a first sub-high-voltage power supply line and a second sub-high-voltage power supply line connected with each other, the second sub-high-voltage power supply line is located on a side of the first sub-high-voltage power supply line away from the base substrate.

Abstract: Disclosed is a pixel circuit arranged in a display substrate, which comprises a first driving mode and a second driving mode. Content displayed in the display substrate comprises multiple display frames. In the first driving mode and the second driving mode, the display frames comprise refresh frames. A signal of a second scanning line is the same as that of a third scanning line. The time of which the signal of the second scanning line is an active level signal comprises a first refresh time period, a second refresh time period and a third refresh time period, which sequentially occur at intervals. During the second refresh time period, a signal of a first scanning line is an inactive level signal. The voltage of a signal at a reset voltage end is a positive voltage, and the voltage of a signal at a first initial voltage end is a negative voltage.

Abstract: Disclosed is a pixel circuit arranged in a display substrate, which comprises a first driving mode and a second driving mode. Content displayed in the display substrate comprises multiple display frames. In the first driving mode and the second driving mode, the display frames comprise refresh frames. A signal of a second scanning line is the same as that of a third scanning line. The time of which the signal of the second scanning line is an active level signal comprises a first refresh time period, a second refresh time period and a third refresh time period, which sequentially occur at intervals. During the second refresh time period, a signal of a first scanning line is an inactive level signal. The voltage of a signal at a reset voltage end is a positive voltage, and the voltage of a signal at a first initial voltage end is a negative voltage.