Abstract: Embodiments of the present application provide a semiconductor structure formation method and a semiconductor structure. The method includes: the substrate including contact region and dummy region, a first bitline structure and a first dielectric layer being formed on the substrate, the first bitline structure and the first dielectric layer defining discrete capacitor contact openings; forming a first sacrificial layer filling the capacitor contact opening; removing, in the dummy region, part of height of the first bitline structure, part of height of the first dielectric layer and part of height of the first sacrificial layer to form a first opening located at top of a second bitline structure, a second dielectric layer and a second sacrificial layer; forming an insulation layer filling the first opening; removing, in the contact region, the first sacrificial layer to form a second opening; and forming a capacitor contact structure located in the second opening.

Abstract: The present disclosure provides a memory device, and a semiconductor structure and a forming method thereof, which includes: providing a substrate, which includes a plurality of bit line structures, forming a cover layer on each of the bit line structures, forming a first insulating layer and a second insulating layer sequentially on a side wall of each cover layer, and filling a space between second insulating layers of two adjacent bit line structures with a conductive contact layer; tops of the conductive contact layers and the second insulating layers are all lower than surfaces of the cover layers and higher than surfaces of the bit line structures; tops of the first insulating layers are flush with those of the conductive contact layers and the second insulating layers; and etching back the conductive contact layers, to form a capacitor contact hole between cover layers of two adjacent bit line structures.

Abstract: There is provided a method for fabricating a semiconductor device. The method includes: forming a plurality of bit line structures spaced on a substrate of the semiconductor device, the plurality of bit line structures extending along a first direction; forming a sacrificial layer between the plurality of bit line structures; placing the semiconductor device in a reaction chamber of an etching apparatus; releasing a carbon source gas into the reaction chamber, and providing an alternative electric field to dissociate the carbon source gas into a plasma carbon source; controlling the plasma carbon source to be deposited on top surfaces of the plurality of bit line structures to form a carbon overcoat; etching the sacrificial layer and a part of the substrate to form a storage node contact hole; and removing the carbon overcoat.

Abstract: A method of forming a semiconductor memory includes: providing comprising a storage area and a peripheral area located outside the storage area, wherein the substrate has and a plurality of bit line contact parts and a plurality of capacitor contact parts located in the storage area, and a peripheral gate contact part and a peripheral circuit contact part located in the peripheral area; forming a plurality of bit lines, and simultaneously forming a peripheral gate; forming a bit line isolation layer, and simultaneously forming a peripheral gate isolation layer; forming a first conductive capacitor layer in contact with the capacitor contact part, and simultaneously forming a first peripheral conductive layer in contact with the peripheral circuit contact part; forming a first air gap in the bit line isolation layer, and simultaneously forming a second air gap in the peripheral gate isolation layer.

Abstract: Embodiments of the present application provide a semiconductor structure formation method and a semiconductor structure. The method includes: the substrate including contact region and dummy region, a first bitline structure and a first dielectric layer being formed on the substrate, the first bitline structure and the first dielectric layer defining discrete capacitor contact openings; forming a first sacrificial layer filling the capacitor contact opening; removing, in the dummy region, part of height of the first bitline structure, part of height of the first dielectric layer and part of height of the first sacrificial layer to form a first opening located at top of a second bitline structure, a second dielectric layer and a second sacrificial layer; forming an insulation layer filling the first opening; removing, in the contact region, the first sacrificial layer to form a second opening; and forming a capacitor contact structure located in the second opening.

Abstract: Embodiments of the present application provide a semiconductor structure formation method and a semiconductor structure. The semiconductor structure formation method includes: providing a substrate, the substrate including a contact region and a virtual region arranged adjacent to each other, a bitline structure and a dielectric layer arranged discretely being formed on the substrate, an extension direction of the dielectric layer intersecting with that of the bitline structure, and the bitline structure and the dielectric layer defining discrete capacitor contact openings; forming a sacrificial layer filling the capacitor contact opening; removing, in the contact region, the sacrificial layer to form a second opening; forming a bottom conductive layer filling the second opening; removing, in the virtual region, some height of the sacrificial layer to form a first opening; forming an insulation layer filling the first opening; and forming a capacitor contact structure located in the second opening.