Abstract: The invention provides a method for detecting miRNA based on polymerase chain reaction comprising EvaGreen dye, and the use of EvaGreen dye in elevating the binding specificity of primers to templates in PCR.

Abstract: Provided are a process for preparing an N ortho acyl substituted nitrogen-containing heterocyclic compound and an aminal iron (II) complex thereof, and the use of the complexes obtained by the process in an olefin oligomerization catalyst. The N ortho acyl substituted nitrogen-containing heterocyclic compound in the present invention is for example 2-acyl-1,10-phenanthroline or 2,6-diacetyl pyridine as shown in formula b, and the N ortho acyl substituted nitrogen-containing heterocyclic compound in the present invention is produced by a reaction of a precursor thereof in a substituted or unsubstituted nitrobenzene. Preferably the precursor shown in formula I in the present invention is produced by 1,10-phenanthroline reacting with trialkyl aluminum, or a halogenoalkyl aluminum RnAIXm, or a substituted or unsubstituted benzyl lithium Ph?CH2Li, followed by hydrolysis.

Abstract: In some aspects, a one-dimensional flow model is generated. The one-dimensional flow model can represent flow of a first fluid and a second fluid in a flow path in a well system environment. The one-dimensional flow model comprises an effective diffusion coefficient model for a composite fluid volume comprising the first and second fluids. The effective diffusion coefficient model calculates an effective diffusion coefficient for the composite fluid volume based on a difference between the respective densities and viscosities of the first fluid and the second fluid.

Abstract: The invention provides a method for detecting miRNA based on polymerase chain reaction comprising EvaGreen dye, and the use of EvaGreen dye in elevating the binding specificity of primers to templates in PCR.

Abstract: Provided are a process for preparing an N ortho acyl substituted nitrogen-containing heterocyclic compound and an aminal iron (II) complex thereof, and the use of the complexes obtained by the process in an olefin oligomerization catalyst. The N ortho acyl substituted nitrogen-containing heterocyclic compound in the present invention is for example 2-acyl-1,10-phenanthroline or 2,6-diacetyl pyridine as shown in formula b, and the N ortho acyl substituted nitrogen-containing heterocyclic compound in the present invention is produced by a reaction of a precursor thereof in a substituted or unsubstituted nitrobenzene. Preferably the precursor shown in formula I in the present invention is produced by 1,10-phenanthroline reacting with trialkyl aluminum, or a halogenoalkyl aluminum RnAlXm, or a substituted or unsubstituted benzyl lithium 2Li, followed by hydrolysis.

Abstract: A kind of pyrazolyl acrylniitrile compounds represented by the structures of formula I or stereoisomers thereof are disclosed in the present invention. Where in: R1 is selected from the group of substituents consisting of H, C1-C4 alkoxy C1-C2 alkyl, C3-C5 alkenyloxy C1-C2 alkyl, C3-C5 alknyloxy C1-C2 alkyl, C1-C4 alkylthio C1-C2 alkyl, C1-C5 alkyl carbonyl, C3-C8 cycloalkyl carbonyl, C1-C5 alkoxy carbonyl or C1-C5 alkylthio carbonyl; R2 is Cl or methyl; R3 is H, methyl, CN, NO2 or halogen. Or its stereoisomers. The Formula I compounds have high insecticidal activities or acaricidal activities, so they can be used as insecticide or acaricide.

Abstract: The present invention provides a catalyst composition for the ethylene oligomerization, which comprises 2-imino-1,10-phenanthroline coordinated iron (II), cobalt (II) or nickel (II) chloride as main catalyst and triethylaluminum as cocatalyst. The present invention also provides a process for oligomerization of ethylene is provided, wherein a catalyst composition comprising 2-imino-1,10-phenanthroline coordinated iron (II), cobalt (II) or nickel (II) chloride as main catalyst and triethylaluminum as cocatalyst is used, and the molar ratio of aluminum in the cocatalyst to central metal in the main catalyst ranges from 30 to less than 200. According to the present invention, another process for oligomerization of ethylene is also provided, wherein a catalyst composition comprising 2-imino-1,10-phenanthroline coordinated iron (II), cobalt (II) or nickel (II) chloride as main catalyst and triethylaluminum as cocatalyst is used, and the temperature of ethylene oligomerization ranges from ?10 to 19° C.

Abstract: A preparation method of phenylcarboxamides of formula (I), the reaction scheme of which is as follows: wherein the groups are defined in the description. In this method, 3-halo-1-(3-chloro-2-pyridinyl)-4,5-dihydro-1H-pyrazole-5-carboxylic acid esters (V) as the raw materials are hydrolyzed to obtain carboxylic acids of formula (IV) under a basic condition, and carboxylic acids (IV) are simultaneously acyl halogenated and oxidated to get acyl halide of formula (III), and then without the presence of a acid binging agent, acyl chlorides (III) are reacted with substituted anilines (II) to get phenylcarboxamides of formula (I) in high yield.

Abstract: A kind of pyrazolyl acrylniitrile compounds represented by the structures of formula I or stereoisomers thereof are disclosed in the present invention. Where in: R1 is selected from the group of substituents consisting of H, C1-C4 alkoxy C1-C2 alkyl, C3-C5 alkenyloxy C1-C2 alkyl, C3-C5 alknyloxy C1-C2 alkyl, C1-C4 alkylthio C1-C2 alkyl, C1-C5 alkyl carbonyl, C3-C8 cycloalkyl carbonyl, C1-C5 alkoxy carbonyl or C1-C5 alkylthio carbonyl; R2 is Cl or methyl; R3 is H, methyl, CN, NO2 or halogen. Or its stereoisomers. The Formula I compounds have high insecticidal activities or acaricidal activities, so they can be used as insecticide or acaricide.

Abstract: A preparation method of phenylcarboxamides of formula (I), the reaction scheme of which is as follows: wherein the groups are defined in the description. In this method, 3-halo-1-(3-chloro-2-pyridinyl)-4,5-dihydro-1H-pyrazole-5-carboxylic acid esters (V) as the raw materials are hydrolyzed to obtain carboxylic acids of formula (IV) under a basic condition, and carboxylic acids (IV) are simultaneously acyl halogenated and oxidated to get acyl halide of formula (III), and then without the presence of a acid binging agent, acyl chlorides (III) are reacted with substituted anilines (II) to get phenylcarboxamides of formula (I) in high yield.

Abstract: A circuit containing a parallel connection of a first sub-circuit and a second sub-circuit is provided. The first sub-circuit comprises a serial connection of a first field effect transistor having a first threshold voltage and a first voltage dividing device. The second sub-circuit comprises a serial connection of a second field effect transistor having a second threshold voltage, which is different from the first threshold voltage, and a second voltage dividing device. The voltage between the first field effect transistor and the first voltage dividing device is compared with the voltage between the second field effect transistor and the second voltage dividing device so that a signal may be generated at a temperature at which the ratio of a performance parameter such as on-current between the first and second field effect transistors crosses over a predefined value. The signal may be advantageously employed to actively control circuit characteristics.

Abstract: A design structure comprising a digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A bus change-over detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal.

Abstract: A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A high-high detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.

Abstract: A digital clock generation circuit (and a method for operating the same). The digital clock generation circuit includes a first, a second, a third differential comparator circuits. The first differential comparator circuit receives the positive differential clock signal and a reference voltage, and generates a first output signal. The second differential comparator circuit receives the positive and negative differential clock signal, and generates a second output signal. The third differential comparator circuit receives the reference voltage and the negative differential clock signal, and generates a third output signal. A high-high detecting circuit receives the first output signal, and the third output signal, and generates an Enable signal. The digital clock generation circuit further includes a latch circuit which receives the second output signal, and the Enable signal and generates a digital clock signal. The latch circuit comprises a latch with glitch or noise immunity.

Abstract: A method and device program a dual edge programmable delay unit, that responds to an input signal with a rise time and a fall time, includes a buffer which receives the input signal and provides an output signal with programmed variable delays between the rise and fall times of the output signal. Programmable control sources (PCS) provide separate control inputs to a buffer. The FTPCS charges a capacitor in the buffer when the input signal changes from high to low to adjust time delay before the fall of the buffer output signal. The RTPCS discharges the capacitor in the buffer when the input signal changes from low to high to adjust time delay before the rise of the buffer output signal.

Abstract: A method and device program a dual edge programmable delay unit, that responds to an input signal with a rise time and a fall time, includes a buffer which receives the input signal and provides an output signal with programmed variable delays between the rise and fall times of the output signal. Programmable control sources (PCS) provide separate control inputs to a buffer. The FTPCS charges a capacitor in the buffer when the input signal changes from high to low to adjust time delay before the fall of the buffer output signal. The RTPCS discharges the capacitor in the buffer when the input signal changes from low to high to adjust time delay before the rise of the buffer output signal.

Abstract: A structure and method for eliminating glitches at the output of a receiver receiving signals sent to one end of a bi-directional, simultaneous transmission line. The receiver comprises two comparators, a logic circuit, a glitch detector, and a programmable delay unit. The two comparators convert a three-state digital signal on the transmission line into two two-state digital signals so that the logic circuit can understand. When a glitch occurs at the output of the logic circuit, also the output of the receiver, caused by the transitions on the output of one of the comparators and a first signal being sent to the other end of the transmission line reaching the logic circuit not at the same time, the glitch detector causes the programmable delay unit to adjust delay to the propagation path of the first signal to the logic circuit so as to eliminate the cause of the glitch.

Abstract: In order to reduce slew rate and minimize delay skew, the invention adds a pull-down booster circuit connected to the gate of the driving transistor and/or a pull-up booster circuit connected the gate of the driving transistor. The pull-down booster circuit is adapted to dynamically pull-down the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from a first voltage (e.g., a logical “0”) to a second voltage (e.g., a logical “1”). The pull-up booster circuit is adapted to dynamically pull-up the voltage at the gate of the driving transistor when the voltage level at the input to the logical enable device changes from the second voltage to the first voltage.

Abstract: An I/O driver comprising: a circuit adapted to be powered by a first power supply. The circuit is adapted to receive a first signal referenced to the voltage of a second power supply and is adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply. The circuit is adapted to maintain the second signal on an output of the I/O driver when the second power supply is powered off.

Abstract: An I/O driver comprising: a circuit adapted to be powered by a first power supply. The circuit is adapted to receive a first signal referenced to the voltage of a second power supply and is adapted to convert the first signal to a second signal of the same logical value as the first signal and referenced to the voltage of the first power supply. The circuit is adapted to maintain the second signal on an output of the I/O driver when the second power supply is powered off.