Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to perform a maintenance operation involving a plurality of hosts of an information handling system cluster by: determining a score for each host based on a sum of working memory sizes for all active virtual machines executing on such host plus a sum of persistent storage sizes for all virtual machines stored on such host; based on the determined scores, selecting a first host for upgrading; migrating at least a portion of all virtual machines stored on the first host from the first host to one or more other hosts; and causing the first host to perform the maintenance operation.

Abstract: A disclosed method may assign, with a DHCP module, two static IP addresses to each of one or more hyper-converged infrastructures nodes. The two static IP addresses may include an out of band IP address for a baseboard management controller (BMC) network interface to an OOB management network and an internal management IP address for a network interface associated with an internal management network. Disclosed methods may then access, for each of the one or more nodes, a BMC at the OOB IP address, to invoke a BMC tool to retrieve cluster configuration information for each node. A dashboard user interface may then be generated, based on the configuration retrieved for each node, and displayed. The cluster configuration information may indicate whether the node is a cluster node, comprising a node assigned to a cluster, or a free node, comprising a node not assigned to a cluster.

Abstract: An information handling system may include at least one processor and a memory. The information handling system may be configured to: receive information regarding equipment that is to be communicatively coupled to a data network; determine a topology for communicatively coupling the equipment to the data network, wherein the topology includes information regarding which equipment ports of the equipment are to be coupled to data network ports of the data network; and transmit information regarding the topology to a user.

Abstract: Provided are a tub assembly and a washing machine. The tub assembly includes an outer tub, and a lining tub disposed in the outer tub fixedly connected to the outer tub. An inner wall of the outer tub is protected by means of the lining tub, thereby preventing the problem of bacteria breeding caused by an inner wall face of the outer tub and washing water being in contact for a long time, or the problem of mildew occurring due to the inner wall of the outer tub being in a damp environment for a long time. The washing effect of a washing machine can be effectively improved, thereby preventing health and hygiene problems, etc.

Abstract: Disclosed is a lithium zirconium-based aluminosilicate glass, comprising the following components by mass percentage: 50%-72% of SiO2, 10%-27% of Al2O3, 0.1%-10.0% of B2O3, 2%-10% of Li2O, 4%-15% of Na2O, 0.1%-5.0% of ZrO2, and 0-4% of K2O, wherein the total mass percentage of Li2O, Na2O and K2O is ?9%, and the ratio of the mass of Li2O to the total mass of Li2O, Na2O and K2O is (0.22-0.48):1.

Abstract: An information handling system may include at least one processor; and a non-transitory memory coupled to the at least one processor. The information handling system may be configured to manage an upgrade of a cluster of N host systems by: receiving an indication of a number M of host systems of the cluster that are needed to satisfy an operational requirement of the cluster; removing N-M of the host systems from the cluster; causing the removed host systems to be upgraded in parallel; and adding at least one of the removed host systems back to the cluster after the at least one of the removed host systems has completed the upgrade.

Abstract: An information handling system may include at least one processor; and a non-transitory memory coupled to the at least one processor. The information handling system may be configured to manage an upgrade of a cluster of N host systems by: receiving an indication of a number M of host systems of the cluster that are needed to satisfy an operational requirement of the cluster; removing N-M of the host systems from the cluster; causing the removed host systems to be upgraded in parallel; and adding at least one of the removed host systems back to the cluster after the at least one of the removed host systems has completed the upgrade.

Abstract: Provided is a common-emitter and common-base heterojunction bipolar transistor disposed on a packaging substrate with a heat sink, including a common-base heterojunction bipolar transistor having a first base, a first emitter and a first collector, a common-emitter heterojunction bipolar transistor having a second base, a second emitter and a second collector, a heat shunt bridge for connecting the first emitter with the second collector, a first pad for being connected with the first base and a first copper pillar, a second pad for being connected with the first collector and a second copper pillar, a third pad for being connected with the second base and a third copper pillar, and a fourth copper pillar disposed above the second emitter; the common-emitter and common-base heterojunction bipolar transistor is flip-chip mounted on the packaging substrate, and the fourth copper pillar is soldered on the heat sink.

Abstract: The application discloses a solar cell component including at least two chip sets connected in series, wherein each chip set includes a plurality of chip units connected in parallel and a bypass diode connected in parallel with the chip units, each chip unit includes one or more photovoltaic chips connected in series, positive poles of the bypass diodes are connected with negative poles of the chip units, and negative poles of the bypass diodes are connected with positive poles of the chip units. The application further provides a solar panel with the solar cell component. The application not only can reduce the number of the bypass diodes, but also can improve economy of the product.

Abstract: Provided is a common-emitter and common-base heterojunction bipolar transistor disposed on a packaging substrate with a heat sink, including a common-base heterojunction bipolar transistor having a first base, a first emitter and a first collector, a common-emitter heterojunction bipolar transistor having a second base, a second emitter and a second collector, a heat shunt bridge for connecting the first emitter with the second collector, a first pad for being connected with the first base and a first copper pillar, a second pad for being connected with the first collector and a second copper pillar, a third pad for being connected with the second base and a third copper pillar, and a fourth copper pillar disposed above the second emitter; the common-emitter and common-base heterojunction bipolar transistor is flip-chip mounted on the packaging substrate, and the fourth copper pillar is soldered on the heat sink.

Abstract: The present disclosure discloses a GaN-based HEMT device, comprising a gate electrode, a source electrode, and a drain electrode, and further comprising a substrate, a buffer layer, a GaN channel layer, a first barrier layer, a second barrier layer and a dielectric passivation layer, the buffer layer being sequentially stacked from bottom to top, wherein an N-type ion injection region is formed in the GaN channel layer and the first barrier layer, the source electrode and the drain electrode are formed on an upper surface of the N-type ion-implanted region; the gate electrode is formed on an upper surface of the first barrier layer and is located between the source electrode and the drain electrode; and the dielectric passivation layer encircles the gate electrode so as to isolate the gate electrode from the N-type ion-implanted region.

Abstract: The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer.

Abstract: The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer.

Abstract: The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an AlxY2-xO3 interface passivation layer formed on the group III-V substrate; and a high dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2?x?1.9. The composite gate dielectric layer modifies the Al/Y ratio of the AlxY2-xO3 interface passivation layer, changes the average number of atomic coordination in the AlxY2-xO3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the AlxY2-xO3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improves tolerance of the dielectric layer on the voltage, and improves the quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.

Abstract: The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an AlxY2-xO3 interface passivation layer formed onthe group III-V substrate; and a high dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2?x?1.9.The composite gate dielectric layer modifies the AI/Y ratio of the AlxY2-xO3 interface passivation layer, changes the average number of atomic coordination in the AlxY2-xO3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the AlxY2-xO3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improvestolerance of the dielectric layer on the voltage, and improvesthe quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.

Abstract: A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.

Abstract: A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.