Abstract: Disclosed are a method for processing neural network feature map using a plurality of accelerators. The method includes: reading first feature data about the neural network feature map from first shift register array in first accelerator among a plurality of neural network accelerators, and first weight data corresponding to the first feature data from first buffer; performing preset operation on the first feature data and first weight data using the first accelerator, to obtain a first operation result; shifting, according to preset shift rule, first overlapping feature data in the first feature data and required by a second accelerator to a second shift register array of the second accelerator; and performing a preset operation on the second feature data from the second shift register array including the first overlapping feature data and the read second weight data using the second accelerator, to obtain a second operation result.

Abstract: Embodiments of the present disclosure disclose a circuit detection method and a data detection circuit. The circuit detection method comprises: if a current time point reaches a preset detection time period, based on a data storage address of a detected module, reading a data to be detected corresponding to the detected module from a storage area corresponding to the data storage address; using a preset calculation method corresponding to the detected module to perform a calculation on the data to be detected to obtain a first calculation result; based on the first calculation result and a preset calculation result corresponding to the data storage address, determining a fault state of the detected module. The embodiments of the present disclosure can detect the storage circuit in a timely and accurate manner without data verification by adding hardware, thereby saving space occupied by the system and reducing power consumption.

Abstract: Disclosed is an apparatus for performing a convolution operation in a convolutional neural network. The apparatus may comprise a selector for selecting one or more nonzero elements of a weight parameter, a selector for selecting a data item(s) corresponding to selected nonzero elements in input feature data, and a calculator unit for performing an operation. The apparatus may realize the convolution operation in a sparsified convolutional neural network efficiently through the hardware.

Abstract: Disclosed are a circuit unit, a circuit module and an apparatus for data statistics. The circuit unit comprises a first register and a second register, and stores data received via a first input terminal in the first register in a case where a first control terminal receives a valid control signal, stores data received via a second input terminal in the second register in a case where a second control terminal receives a valid control signal, and increases the value of data stored in the second register by 1 in a case where a third control terminal receives a valid control signal. The circuit module comprises one or more such circuit units, and the apparatus comprises one or more such circuit modules. The circuit module or the apparatus may use smaller resource and smaller power consumption to complete data statistics.

Abstract: Embodiments of the present disclosure disclose a circuit detection method and a data detection circuit. The circuit detection method comprises: if a current time point reaches a preset detection time period, based on a data storage address of a detected module, reading a data to be detected corresponding to the detected module from a storage area corresponding to the data storage address; using a preset calculation method corresponding to the detected module to perform a calculation on the data to be detected to obtain a first calculation result; based on the first calculation result and a preset calculation result corresponding to the data storage address, determining a fault state of the detected module. The embodiments of the present disclosure can detect the storage circuit in a timely and accurate manner without data verification by adding hardware, thereby saving space occupied by the system and reducing power consumption.

Abstract: A method, an apparatus, and an electronic device for controlling memory access are disclosed. According to an embodiment, there is provided a method for controlling access to a memory including a plurality of memory modules configured in parallel. The method comprises: receiving an access instruction including an addressing field which comprise a parallel control field for controlling parallel access, a module address field for indicating a memory module, and an in-module address field for indicating an addresses within a memory module; parsing the access instructions to determine the parallel control field, the module address field and the in-module address field; determining one or more memory modules to be accessed based on the parallel control field and the module address field; and accessing one or more addresses which are within the one or more memory modules to be accessed and assigned by the in-module address field.

Abstract: A method, an apparatus, and an electronic device for controlling memory access are disclosed. According to an embodiment, there is provided a method for controlling access to a memory including a plurality of memory modules configured in parallel. The method comprises: receiving an access instruction including an addressing field which comprise a parallel control field for controlling parallel access, a module address field for indicating a memory module, and an in-module address field for indicating an addresses within a memory module; parsing the access instructions to determine the parallel control field, the module address field and the in-module address field; determining one or more memory modules to be accessed based on the parallel control field and the module address field; and accessing one or more addresses which are within the one or more memory modules to be accessed and assigned by the in-module address field.

Abstract: Disclosed are a circuit unit, a circuit module and an apparatus for data statistics. The circuit unit comprises a first register and a second register, and stores data received via a first input terminal in the first register in a case where a first control terminal receives a valid control signal, stores data received via a second input terminal in the second register in a case where a second control terminal receives a valid control signal, and increases the value of data stored in the second register by 1 in a case where a third control terminal receives a valid control signal. The circuit module comprises one or more such circuit units, and the apparatus comprises one or more such circuit modules. The circuit module or the apparatus may use smaller resource and smaller power consumption to complete data statistics.

Abstract: Disclosed is an apparatus for performing a convolution operation in a convolutional neural network. The apparatus may comprise a selector for selecting one or more nonzero elements of a weight parameter, a selector for selecting a data item(s) corresponding to selected nonzero elements in input feature data, and a calculator unit for performing an operation. The apparatus may realize the convolution operation in a sparsified convolutional neural network efficiently through the hardware.