Abstract: The present invention provides a structure and a method of reinforcing a conductor soldering point of a semiconductor device. The structure includes an inner frame lead, a soldering area arranged on the surface of the inner frame lead, a conductor soldered in the soldering area, and a locking card including a pressing part, a locking part overhangs outwards from the pressing part pressed on the conductor. The locking part penetrates through the inner frame lead and is clamped on the side of the inner frame lead deviating from the conductor. According to the present invention, the conductor soldered on the inner frame lead is firmly clamped on the inner frame lead through the locking card to effectively avoid the stripping condition of the conductor and the inner frame lead, reinforce the electrical connection of the conductor and the inner frame lead, and improve the reliability of the semiconductor device.

Abstract: A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate.

Abstract: A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate.

Abstract: Disclosed are metal alloy materials comprising iodine adsorbed onto the catalyst surface exhibiting surprisingly improved performance and durability in comparison with known electrocatalysts. Methods of preparation of the catalysts and methods of use thereof are also described.

Abstract: A semiconductor device package and packaging method, the semiconductor device packaging method comprising: providing a chip with a bonding pad formed on the chip surface; forming a passivation layer and a bump on the chip surface, wherein the passivation layer has an opening exposing part of the pad, the bump is located in the opening and the size of the bump is less than the size of the opening; forming a solder ball covering the top surface and the side wall of the bump, and the bottom surface of the opening. The formed semiconductor device package is not easy to form a short circuit. The bonding strength between the solder ball and the bump is high and the performance of the semiconductor device is stable.

Abstract: A semiconductor device package and packaging method, the semiconductor device packaging method comprising: providing a chip with a bonding pad formed on the chip surface; forming a passivation layer and a bump on the chip surface, wherein the passivation layer has an opening exposing part of the pad, the bump is located in the opening and the size of the bump is less than the size of the opening; forming a solder ball covering the top surface and the side wall of the bump, and the bottom surface of the opening. The formed semiconductor device package is not easy to form a short circuit. The bonding strength between the solder ball and the bump is high and the performance of the semiconductor device is stable.

Abstract: Embodiments of the present invention provide an array substrate, a method for repairing the array substrate and a display apparatus. The array substrate comprises: a thin film transistor; a pixel electrode; a gate line and a data line crossing with each other; and a repairing layer connected electrically to the pixel electrode, wherein the repairing layer has an area within a preset area range of the repairing layer which depends on an area of a repairing light spot, and wherein the repairing layer has a pattern comprising at least one hollow portion.

Abstract: Embodiments of the present invention provide an array substrate, a method for repairing the array substrate and a display apparatus. The array substrate comprises: a thin film transistor; a pixel electrode; a gate line and a data line crossing with each other; and a repairing layer connected electrically to the pixel electrode, wherein the repairing layer has an area within a preset area range of the repairing layer which depends on an area of a repairing light spot, and wherein the repairing layer has a pattern comprising at least one hollow portion.

Abstract: A 3D system-level packaging method includes providing a packaging substrate, forming a glue layer on the substrate, and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer. The method also includes forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, and each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers.

Abstract: A line detecting apparatus and a line detecting method for an array substrate relates to the field of line detecting technology. The detecting method comprises: arranging an input terminal sensor (30) at a signal input terminal of a wire to be detected, arranging one output terminal sensor (40, 41, 42, 43) at a signal output terminal of the wire to be detected, and arranging other output terminal sensor (40, 41, 42, 43) at a signal output terminal of another wire adjacent to the wire to be detected; measuring an output voltage of the wire to be detected by a voltage detector; and determining the line conduction condition of the wire to be detected according to the output voltage as measured. When the sensors perform line scan, the coordinate of the specific location where the short-circuit or open-circuit occurs can be found directly without performing scan by PDS or AOI, thus simplifying the technical processes, shortening the time for detecting, and saving the production cost.

Abstract: A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate.

Abstract: A 3D system-level packaging method includes providing a packaging substrate, forming a glue layer on the substrate, and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer. The method also includes forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, and each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers.

Abstract: The present invention discloses a method for recognizing a handwritten character, which includes the following steps of: obtaining a coarse classification template and a fine classification template; receiving a handwritten character input signal from a user, gathering a discrete coordinate sequence of trajectory points of the inputted character, and pre-processing the discrete coordinate sequence; extracting eigenvalues and calculating a multi-dimensional eigenvector of the inputted character; matching the inputted character with the coarse classification template to select a plurality of the most similar candidate character classes; and matching the eigen-transformed inputted character with sample centers of the candidate character classes selected from the fine classification template, and determining the most similar character classes among the candidate character classes. The present invention further discloses a system for recognizing a handwritten character.

Abstract: The present invention discloses a method for recognizing a handwritten character, which includes the following steps of: obtaining a coarse classification template and a fine classification template; receiving a handwritten character input signal from a user, gathering a discrete coordinate sequence of trajectory points of the inputted character, and pre-processing the discrete coordinate sequence; extracting eigenvalues and calculating a multi-dimensional eigenvector of the inputted character; matching the inputted character with the coarse classification template to select a plurality of the most similar candidate character classes; and matching the eigen-transformed inputted character with sample centers of the candidate character classes selected from the fine classification template, and determining the most similar character classes among the candidate character classes. The present invention further discloses a system for recognizing a handwritten character.

Abstract: A first medium having an acousto-optic activity and a second medium are combined to form a net medium having a net acousto-optic activity greater than the acousto-optic activity of the first medium, where the improvement is substantiated via measurements made at specific viewing conditions, and where the second medium can be chosen because it effects at least one of three key properties of the net medium.

Abstract: A product and method uses acousto-optic reflection-active media having an optical reflectivity which changes with changes in acoustic energy intensity interacting with the media to form images of defects in samples when the defects reflect acoustic energy differently from known acoustically reflecting parts of the samples.

Abstract: A product and method uses acousto-optic reflection-active media having an optical reflectivity which changes with changes in acoustic energy intensity interacting with the media to form images of defects in samples when the defects reflect acoustic energy differently from known acoustically reflecting parts of the samples.

Abstract: A computer-readable signal bearing medium (10) has components (11, 21, 31) which act via a data processor (86) in an imaging system having an acoustic energy source (81) and a birefringent detector (84, 70) to record first data (14) from a first portion (61) of an object (60), the first portion attenuating first acoustic energy (12) at least part way to a first attenuation maximum (13, 43) along a first acousto-optic response (41) of the birefringent detector; to record second data (24) from a second portion (62) of the object, the second portion attenuating second acoustic energy (22) at least part way to a second attenuation maximum (23, 53) along a second acousto-optic response (51) of the birefringent detector; combines the data (32), and outputs a result.

Abstract: An ultrasonic inspection system for inspecting a test object and producing substantially artifact-free images, which system includes (1) a sound source for emitting ultrasonic energy toward a test object, (2) a liquid crystal detector for detecting emitted ultrasonic energy and displaying an image, and (3) a coupling medium for sonically coupling the sound source, the test object and the detector. The ultrasonic energy is emitted at each of a plurality of frequencies within a predetermined range. It has been determined that the ultrasonic energy insonifing the object can be caused to scan the object and be angularly varied with respect thereto. Moreover, the rate of frequency scanning is substantially less that the detector image decay so as to produce a substantially flicker-free image. The angular variation is performed by rocking the sound source through a small angle, such as 2.degree. to 6.degree. relative to the liquid crystal detector.