Abstract: Provided are novel selectable markers and uses thereof. Specifically, provided are uses of nucleotide sequences encoding a glutamine synthetase (GS) derived from Alligator, green anole, or spotted gar as selectable markers for identifying genomic loci with high transcriptional activity or host cells having high productivity of a protein of interest, and/or for accelerating the identification process. Related methods of screening, methods of production, and expression systems are also included.

Abstract: A data processing circuit is disclosed. The data processing circuit relates to the field of digital circuits, and includes a first computing circuit and an input control circuit. The first computing circuit includes one or more computing sub-circuits. Each computing sub-circuit includes a first addition operation circuit, a multiplication operation circuit, a first comparison operation circuit, and a first nonlinear operation circuit. The first nonlinear operation circuit includes at least one of an exponential operation circuit and a logarithmic operation circuit. The input control circuit is configured to: control the first computing circuit to read input data and an input parameter, and control, according to a received first instruction, the operation circuit in the computing sub-circuit included in the first computing circuit, to perform an operation on the input data and the input parameter.

Abstract: This application relates to a data format conversion apparatus and method. The data format conversion apparatus is located in a DMA module of a processor. A data format that is of tensor data and that is supported by the processor is a first data format. The DMA module includes: a DMA controller DMAC. If a second data format of tensor data stored in an external memory is different from the first data format, the DMAC is configured to convert, in a process of transmitting to-be-converted tensor data between a memory of the processor and the external memory, the to-be-converted tensor data from the first data format into the second data format or from the second data format into the first data format, to obtain converted tensor data.

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

Abstract: A data processing method and apparatus are disclosed. In various embodiments, R groups of proposal region sequences are obtained. Each group of proposal region sequence includes a plurality of proposal regions. In those embodiments, a VRPAC instruction is invoked to calculate an area of each proposal region in each group of proposal region sequence. For a jth group of proposal region sequence in the R groups of proposal region sequences, a VIOU instruction and a VAADD instruction are invoked to determine j suppression matrices of the jth group of proposal region sequence and determine a suppression vector of the jth group of proposal region sequence based on the j suppression matrices. In those embodiments, an unsuppressed proposal region is determined based on a suppression vector of each group of proposal region sequence.

Abstract: A neural network accelerator is provided, including: a preprocessing module (301), configured to perform first forward winograd transform on a target matrix corresponding to an input feature map, to obtain a transformed target matrix, where the preprocessing module (301) is further configured to perform second forward winograd transform on a convolution kernel, to obtain a transformed convolution kernel; a matrix operation module (302), configured to perform a matrix multiplication operation on a first matrix and a second matrix, to obtain a multiplication result, where the first matrix is constructed based on the transformed target matrix, and the second matrix is constructed based on the transformed convolution kernel; and a vector operation module (303), configured to perform inverse winograd transform on the multiplication result, to obtain an output feature map.

Abstract: A neural network scheduling method and apparatus are provided One example method includes: determining a first batch size corresponding to each layer of one or more layers in a neural network; forming, through grouping based on the first batch size, the neural network into a neural network including at least one first layer group forming, through grouping based on a grouping result of the first layer group, the neural network into a neural network including at least one second layer group and scheduling the neural network based on a grouping result of the second layer group.

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

Abstract: A data processing circuit is disclosed. The data processing circuit relates to the field of digital circuits, and includes a first computing circuit and an input control circuit. The first computing circuit includes one or more computing sub-circuits. Each computing sub-circuit includes a first addition operation circuit, a multiplication operation circuit, a first comparison operation circuit, and a first nonlinear operation circuit. The first nonlinear operation circuit includes at least one of an exponential operation circuit and a logarithmic operation circuit. The input control circuit is configured to: control the first computing circuit to read input data and an input parameter, and control, according to a received first instruction, the operation circuit in the computing sub-circuit included in the first computing circuit, to perform an operation on the input data and the input parameter.

Abstract: A data processing method and apparatus are disclosed. The method includes: obtaining R groups of proposal region sequences, where each group of proposal region sequence includes a plurality of proposal regions; invoking a VRPAC instruction to calculate an area of each proposal region in each group of proposal region sequence; for a jth group of proposal region sequence in the R groups of proposal region sequences, invoking a VIOU instruction and a VAADD instruction to determine j suppression matrices of the jth group of proposal region sequence and determine a suppression vector of the jth group of proposal region sequence based on the j suppression matrices; and determining an unsuppressed proposal region based on a suppression vector of each group of proposal region sequence. The method reduces invoked instructions, reduces instruction execution steps, and shortens a time used in NMS calculation.

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

Abstract: A convolution operation chip (300) and a communications device are provided. The convolution operation chip (300) includes: an M×N multiplication accumulator array (320), including a first multiplication accumulation window, where a processing element PEX,Y of the first multiplication accumulation window is configured to: perform a multiplication operation on convolutional data of the PEX,Y and a convolutional parameter of the PEX,Y, transmit the convolutional parameter of the PEX,Y to a PEX,Y+1, transmit the convolutional data of the PEX,Y to a PEX?1,Y+1, and respectively use the convolutional parameter of the PEX,Y and the convolutional data of the PEX,Y as multipliers of multiplication operations performed by the PEX,Y+1 and the PEX?1,Y+1; a data cache module (310), configured to transmit convolutional data and a convolutional parameter to the first multiplication accumulation window; and an output control module (330), configured to output a convolutional result.

Abstract: A data processing method is disclosed, the method includes: receiving a request message that is sent from a host service layer and transparently transmitted through a host driver layer, where the request message includes at least one acceleration type identifier and to-be-acceleratedly-processed service data, and each acceleration type identifier corresponds to one type of accelerated processing; and performing at least one type of accelerated processing in a one-to-one correspondence with the at least one acceleration type identifier on the service data. In the method, interaction between the host service layer and the hardware processing unit does not need coordination of a specialized driver, so that dependence on a specific underlying driver for a service layer may be shielded.

Abstract: A data processing method is disclosed, the method includes: receiving a request message that is sent from a host service layer and transparently transmitted through a host driver layer, where the request message includes at least one acceleration type identifier and to-be-acceleratedly-processed service data, and each acceleration type identifier corresponds to one type of accelerated processing; and performing at least one type of accelerated processing in a one-to-one correspondence with the at least one acceleration type identifier on the service data. In the method, interaction between the host service layer and the hardware processing unit does not need coordination of a specialized driver, so that dependence on a specific underlying driver for a service layer may be shielded.