Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer.

Abstract: Disclosed is a thin film transistor substrate which facilitates to improve output and transfer characteristics of thin film transistor, wherein the thin film transistor substrate comprises a thin film transistor comprising a lower gate electrode on a substrate, an active layer on the lower gate electrode, source and drain electrodes on the active layer, and an upper gate electrode on the source electrode, drain electrode and active layer, the upper gate electrode for covering a channel region defined by the source and drain electrodes; and a contact portion for electrically connecting the lower gate electrode with the upper gate electrode.

Abstract: A thin film transistor substrate provided with two gate electrodes comprises a thin film transistor including a first gate electrode formed on the substrate; an active layer formed on the first gate electrode; first and second electrodes formed on the active layer; and a second gate electrode formed on the first electrode, the second electrode, and the active layer, wherein the second gate electrode is provided with an opening formed in an area corresponding to at least a part of the second electrode.

Abstract: In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer.

Abstract: A method for fabricating a semiconductor device includes sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern forming a conductive mask pattern including a first opening on the insulating film, forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film, removing the conductive mask pattern, and forming a passivation film along a side wall of the via-hole after removing the conductive mask pattern.

Abstract: Disclosed is a thin film transistor substrate which facilitates to improve output and transfer characteristics of thin film transistor, wherein the thin film transistor substrate comprises a thin film transistor comprising a lower gate electrode on a substrate, an active layer on the lower gate electrode, source and drain electrodes on the active layer, and an upper gate electrode on the source electrode, drain electrode and active layer, the upper gate electrode for covering a channel region defined by the source and drain electrodes; and a contact portion for electrically connecting the lower gate electrode with the upper gate electrode.

Abstract: Disclosed is a thin film transistor substrate which facilitates to improve output and transfer characteristics of thin film transistor, wherein the thin film transistor substrate comprises a thin film transistor comprising a lower gate electrode on a substrate, an active layer on the lower gate electrode, source and drain electrodes on the active layer, and an upper gate electrode on the source electrode, drain electrode and active layer, the upper gate electrode for covering a channel region defined by the source and drain electrodes; and a contact portion for electrically connecting the lower gate electrode with the upper gate electrode.

Abstract: A gate drive circuit for a display device is disclosed, by which output states of scan pulses are identically maintained in a manner of minimizing load deviation between connecting units. The present disclosure includes at least two clock transmission lines transmitting at least two clock pulses having a phase difference in-between, a shift register outputting scan pulses sequentially based on the clock pulses transmitted from the clock transmission lines, and a plurality of connecting units connecting the clock transmission lines to the shift register, respectively, wherein at least one of the connecting units is zigzagged in part, the at least one connecting unit comprising: a pad connected to the corresponding clock transmission line via a pad connecting unit; a zigzagged line connected to one side of the pad; and a connecting line that has one side connected to the zigzagged line and the other side connected to the shift register.

Abstract: A thin film transistor substrate provided with two gate electrodes comprises a thin film transistor including a first gate electrode formed on the substrate; an active layer formed on the first gate electrode; first and second electrodes formed on the active layer; and a second gate electrode formed on the first electrode, the second electrode, and the active layer, wherein the second gate electrode is provided with an opening formed in an area corresponding to at least a part of the second electrode.

Abstract: A method for fabricating a semiconductor device includes sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern forming a conductive mask pattern including a first opening on the insulating film, forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film, removing the conductive mask pattern, and forming a passivation film along a side wall of the via-hole after removing the conductive mask pattern.

Abstract: A display device, which includes a plurality of pixels; a data driver for outputting data signals to the pixels; a bias current outputting unit for outputting a bias current having a predetermined magnitude; a plurality of driving current outputting units for outputting driving currents to the pixels; and a first switch connected between the bias current outputting unit and the driving current outputting units for selecting one of the driving current outputting units to connect to the bias current outputting unit, wherein the magnitudes of the driving currents are substantially the same as a magnitude of the bias current.

Abstract: Disclosed is a gate shift register, which can perform a bi-directional shift operation with a reduced number of switching devices. The gate shift register includes a plurality of stages to receive a plurality of gate shift clocks and sequentially output a scan pulse. A kth stage includes a scan direction controller including first and second forward TFTs and first and second reverse TFTs to convert a scan direction in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller including first to eighteenth TFTs to control charging and discharge operations of Q1, Q2, QB1 and QB2 nodes, and an output unit including first and second pull-up TFTs and first to fourth pull-down TFTs to output two scan pulses based on voltage levels of the Q1, Q2, QB1 and QB2 nodes.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Abstract: Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

Abstract: Disclosed is a thin film transistor substrate which facilitates to improve output and transfer characteristics of thin film transistor, wherein the thin film transistor substrate comprises a thin film transistor comprising a lower gate electrode on a substrate, an active layer on the lower gate electrode, source and drain electrodes on the active layer, and an upper gate electrode on the source electrode, drain electrode and active layer, the upper gate electrode for covering a channel region defined by the source and drain electrodes; and a contact portion for electrically connecting the lower gate electrode with the upper gate electrode.

Abstract: A driving circuit of a liquid crystal display includes: a timing controller to output a gate control signal and a data control signal to control driving of a gate driving unit and a data driving unit and to output digital video data; a pair of gate driving units to be alternately driven by using at least one frame as a period to supply gate signals to gate lines of a liquid crystal panel in response to the gate control signal; and a data driving unit to supply pixel signals to data lines of the liquid crystal panel in response to the data control signal. Degradation of characteristics of transistors constituting each gate driver can be prevented.

Abstract: A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.

Abstract: Disclosed is a gate shift register, which can perform a bi-directional shift operation with a reduced number of switching devices. The gate shift register includes a plurality of stages to receive a plurality of gate shift clocks and sequentially output a scan pulse. A kth stage includes a scan direction controller including first and second forward TFTs and first and second reverse TFTs to convert a scan direction in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller including first to eighteenth TFTs to control charging and discharge operations of Q1, Q2, QB1 and QB2 nodes, and an output unit including first and second pull-up TFTs and first to fourth pull-down TFTs to output two scan pulses based on voltage levels of the Q1, Q2, QB1 and QB2 nodes.

Abstract: The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.