Abstract: A method for preparing (S)-nicotine by reduction includes conducting a reduction process on an alkene compound as shown in Formula I and/or an iminium cation compound as shown in Formula II, thereby producing (S)-nicotine. The method is simple, safe, reliable, and yields both high purity and high quantities of (S)-nicotine production.

Abstract: Disclosed is a cartridge-type rivet feeding mechanism of a flow drill screwing device including a rivet box, a magazine for storing rivets from the rivet box, a rivet pulling mechanism including a rivet pulling block, a rivet pulling block guide housing and a linear driving unit connected with the rivet pulling block, a blowing mechanism including a curved connecting tube and a third air inlet, the rivet pulling block is defined with a T-shaped through hole capable of accommodating a rivet and configured for transferring the rivet from the first connecting tube to the second connecting tube. The first air inlet and the second air inlet are both configured for introducing compressed air to push the rivet to move towards the riveter head.

Abstract: A current integration-based in-memory spiking neural network (SNN) uses charge-domain computation which is naturally compatible with working mechanisms of neurons. In one aspect, silicon-based SRAM cells are included in memory cells of a synaptic array, which can avoid non-idealities caused by resistive NVM materials. Additionally, a modified NVM cell is provided, which benefits from the in-memory SNN architecture design. When SRAM cells are used as memory cells in the synaptic array, post-neuron circuits are designed accordingly so that the in-memory SNN architecture can be used in computation with multi-bit synaptic weights by combining a programmable number of columns. Further, for computation with multi-bit synaptic weights, a circuit is designed to be time-multiplexed for resource sharing to achieve improved area and energy efficiency.

Abstract: A mixed-signal in-memory computing sub-cell only requires 9 transistors for 1-bit multiplication. A computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and a common transistor. A MAC array for performing MAC operations, includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. A differential version of the MAC array provides improved computation error tolerance and an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, allowing the computing module to have a reduced area and suffer from fewer computational errors.

Abstract: An on-chip adaptive optical receiver system, an optical chip, and a communication device are disclosed, which are applied to optical communication. The on-chip adaptive optical receiver system includes an antenna array configured for separating received spatial light to obtain a plurality of sub-light spots; an optical phased array configured for performing phase-shifting processing and beam combining processing on the sub-light spots to obtain combined light; and an optical receiving module configured for demultiplexing the combined light to obtain beacon light. The optical receiving module is further configured for detecting intensity information of the beacon light and generating a feedback signal according to the intensity information.

Abstract: In one aspect, a time division interleaving band-pass filter can be used in voice activity detection, which operates at different central frequencies in respective intervals of a predetermined period of time. The band-pass filter circuitry includes multiple band-pass filtering channels sharing a common transistor circuit, bias circuit and current mirror circuit. The multiple band-pass filtering channels operate in a time division interleaving manner, which enables the sharing of the common set of band-pass filter circuitry components. Thus, the present invention allows a reduced chip area as the area does not increase proportionally with the number of filtering channels. The invention also mitigates the influence of transistor fabrication variations on the filter's central frequencies.

Abstract: A method and system for generating test cases for visual train positioning are provided and relate to the technical field of train positioning. The method includes: first obtaining real environment images around a train, and classifying the real environment images based on blur types; training a generative adversarial network (GAN)-based image generation network with each non-blurred training image, each blurred training image of any blur type in a same scenario and a preset blur type as inputs, and a reconstructed blurred image and a corresponding blur type as outputs, to obtain an image generation model; then inputting each real non-blurred image and target reference data into the image generation model to generate a target reconstructed blurred image, and then deleting target reconstructed blurred images with structural similarities lower than a set threshold.

Abstract: A method for trains to establish a virtual coupling (VC) operation mode, which includes: successively determining whether adjacent preceding and following trains on a same line meet initial conditions and formation conditions of the VC; and performing VC on both trains meeting the initial conditions and formation conditions, and determining the VC of all trains on the line through the above determination method to obtain an overall VC. The method further including controlling operation of a leading train in the overall VC according to driving permission of the VC, and controlling operation of each of remaining following trains based on communication with the corresponding adjacent preceding train in combination with the following train's own driving information. An establishment process of forming a VC operation mode, thereby improving efficiency of train transportation and flexibility of organization and scheduling.

Abstract: A method for implementing a neural network accelerator using only on-chip memory is provided. The method includes: according to a current neural network model, determining a layer having a minimum value of an output feature map in a neural network (101); determining a quantity of layers of pipeline computing (102); determining a quantity of PEs used for pipeline computing (103); applying for a PE and storing an output feature map of the last layer of pipeline computing in on-chip memory (104), releasing a PE corresponding to a layer at which pipeline computing is completed (105), and repeating the above process at a layer at which computing is to be performed until pipeline computing is completed at all layers of the entire neural network. A neural network accelerator using only on-chip memory is further provided, including a controller, a loading module, a computing array, a post processing module, a storage module, and an on-chip buffer.

Abstract: Disclosed in the present invention is An annotation method of arbitrary-oriented rectangular bounding box, wherein: the elements for annotation being: the coordinates of the center point C, a vector {right arrow over (CD)} formed by the center point C and a chosen vertex D, and the ratio of the vector {right arrow over (CP)} to vector {right arrow over (CD)}, where {right arrow over (CP)} is the projection of the vector {right arrow over (CE)} to {right arrow over (CD)}, and {right arrow over (CE)} is a vector formed by the center of the bounding box to one of the vertex E that close neighbor to vertex D; and it is also required that the vector {right arrow over (CP)} is in the same direction as the vector {right arrow over (CD)}, the vertex E in either of the clockwise or counterclockwise direction of the vertex D.

Abstract: A mixed-signal in-memory computing sub-cell only requires 9 transistors for 1-bit multiplication. A computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and a common transistor. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is a differential version of the MAC array with improved computation error tolerance and an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, thus allowing the computing module to have a reduced area and suffer from less computation errors. Also proposed is a method of fully taking advantage of data sparsity to lower the ADC block's power consumption.

Abstract: In one aspect, a time division interleaving band-pass filter can be used in voice activity detection, which operates at different central frequencies in respective intervals of a predetermined period of time. The band-pass filter circuitry includes multiple band-pass filtering channels sharing a common transistor circuit, bias circuit and current mirror circuit. The multiple band-pass filtering channels operate in a time division interleaving manner, which enables the sharing of the common set of band-pass filter circuitry components. Thus, the present invention allows a reduced chip area as the area does not increase proportionally with the number of filtering channels. The invention also mitigates the influence of transistor fabrication variations on the filter's central frequencies.

Abstract: A mixed-signal in-memory computing sub-cell requires only 9 transistors for 1-bit multiplication. In one aspect, there is a computing cell is constructed from a plurality of such sub-cells that share a common computing capacitor and common transistors. As a result, the average number of transistors in each sub-cell is close to 6. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is a differential version of the MAC array with improved computation error tolerance. Also proposed is an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, thus allowing the computing module to have a reduced area and suffer from less computation errors.

Abstract: Disclosed is a method for automatically determining quality of a self-piercing riveting process, including the following operations: inputting standard values, acquiring data in real-time, and comparing data and determining quality of riveting. Riveting parameters and process curves are obtained in real time by a data acquisition system, the measured values for determining quality of riveting is calculated according to the real-time change of the riveting force curve and information of the riveted plates, the quality of the riveting process can be automatically determined by comparing the measured values and the standard values, the efficiency of monitoring quality is improved, inspection of all riveting points can be realized, abandonment of white vehicle bodies due to poor riveting quality is greatly reduced, and the problem that a large number of white vehicle bodies with defective quality cannot be found is avoided, and the riveting quality of the white vehicle bodies is guaranteed.

Abstract: Disclosed is a cartridge-type rivet feeding mechanism of a flow drill screwing device including a rivet box, a magazine for storing rivets from the rivet box, a rivet pulling mechanism including a rivet pulling block, a rivet pulling block guide housing and a linear driving unit connected with the rivet pulling block, a blowing mechanism including a curved connecting tube and a third air inlet, the rivet pulling block is defined with a T-shaped through hole capable of accommodating a rivet and configured for transferring the rivet from the first connecting tube to the second connecting tube. The first air inlet and the second air inlet are both configured for introducing compressed air to push the rivet to move towards the riveter head.

Abstract: Provided herein is technology relating to automated driving and particularly, but not exclusively, to systems comprising roadside intelligent units (RIU) and infrastructure of specific intelligence levels and related methods for providing and/or supplementing automated driving capabilities of connected and automated vehicles (CAV).

Abstract: A Region Merging image segmentation algorithm based on boundary extraction is disclosed, comprising the steps of calculating a gradient image, extracting a boundary and carrying out initial segmentation and Region Merging, wherein each pixel is regarded as one region when initial segmentation is not conducted. In the Region Merging process, the portion of the common boundary of two adjacent regions that lies on the boundary image is taken as the merging cost, the regions are merged according to the ascending order of the mean gradient value inside the region, and a texture difference evaluation mechanism is introduced to reduce the wrong segmentation. The algorithm solves the problems of the other current segmentation algorithms, such as over-segmentation, easy to be influenced by noise and illumination, large in computation and memory consumption, in need of a large number of samples being marked manually and the like.

Abstract: A Region Merging image segmentation algorithm based on boundary extraction is disclosed, comprising the steps of calculating a gradient image, extracting a boundary and carrying out initial segmentation and Region Merging, wherein the initial segmentation can be omitted. In the Region Merging process, the ratio of the length of boundary extraction result lies on the adjacent edge between adjacent regions to the length of the adjacent edge is taken as the merging cost, the regions are merged according to the ascending order of the mean gradient value in the region, and a texture difference evaluation mechanism is introduced to remove the error segmentation. The algorithm solves the problems of the other current segmentation algorithms, such as over-segmentation, easy to be influenced by noise and illumination, large in computation and memory consumption, in need of a large number of samples being marked manually and the like.

Abstract: The present invention relates to compositions comprising salt of acyl glutamate as primary surfactant or primary anionic surfactant and specific structurant polymers.

Abstract: The present invention relates to compositions which comprise salt of acyl glutamate as primary surfactant or primary anionic surfactant and which compositions are clear, low pH isotropic composition.