Abstract: The present disclosure discloses a circuit structure. The circuit structure comprises: a redundant memory device for simulating a read operation of the memory cell in response to the driving of the test word line voltage; a decision device connected to the internal node of the redundant memory device for determining whether the test word line voltage causes the internal node of the redundant memory device to reverse during the read operation in response to the read operation. In response to the reversal, the redundant memory device simulates the read operation with the adjusted test word line voltage until the determination device determines that the internal node does not reverse during the read operation. The circuit structure also comprises: a statistics device for counting and outputting the number of reversals, which is used to characterize the critical word line voltage in conjunction with each adjustment of the test word line voltage.

Abstract: The present disclosure discloses a circuit structure. The circuit structure comprises: a redundant memory device for simulating a read operation of the memory cell in response to the driving of the test word line voltage; a decision device connected to the internal node of the redundant memory device for determining whether the test word line voltage causes the internal node of the redundant memory device to reverse during the read operation in response to the read operation. In response to the reversal, the redundant memory device simulates the read operation with the adjusted test word line voltage until the determination device determines that the internal node does not reverse during the read operation. The circuit structure also comprises: a statistics device for counting and outputting the number of reversals, which is used to characterize the critical word line voltage in conjunction with each adjustment of the test word line voltage.