Abstract: A switch apparatus, includes: a base module including a base case, and a moving magnet movably mounted in the base case; and a manipulation module including a manipulation case, and a first magnet fixedly mounted in the manipulation case, wherein the moving magnet moves between a hold position and a releasable position, the hold position refers to a position in which the manipulation module is held onto the base module as an attractive force acts between the moving magnet and the first magnet, and the releasable position refers to a position in which the manipulation module is releasable from the base module as a repulsive force acts between the moving magnet and the first magnet.

Abstract: An embodiment composition for solid electrolyte membranes of all-solid-state batteries includes a sulfide-based solid electrolyte and a cross-linking agent including two or more acrylate functionalities. An embodiment method of manufacturing a solid electrolyte membrane for an all-solid-state battery includes forming a composition including a sulfide-based solid electrolyte and a cross-linking agent including two or more acrylate functionalities and cross-linking the composition.

Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: A display device includes a display panel having a folding axis extending in a first direction; and a panel supporter disposed on a surface of the display panel. The panel supporter includes a first layer including a first base resin and first fiber yarns extending in the first direction and dispersed in the first base resin, a second layer disposed on the first layer, the second layer including a second base resin and second fiber yarns extending in a second direction intersecting the first direction and dispersed in the second base resin, and a third layer disposed on the second layer, the third layer including a third base resin and third fiber yarns extending in the first direction and dispersed in the third base resin.

Abstract: A three-dimensional information acquisition system using pitching practice, and a method for calculating camera parameters are disclosed. The method by which a server calculates camera parameters in order to obtain three-dimensional information, according to various embodiments of the present invention, can comprise the steps of: receiving, from at least two camera devices, image information of dynamic objects moving at a predetermined speed; confirming location information of each dynamic object, included in the image information, on the basis of the same time in each piece of image information received from each camera device; and calculating camera parameters, which indicate the relationship between the camera devices, by using at least a part of each piece of confirmed location information as a corresponding point.

Abstract: A three-dimensional information acquisition system using pitching practice, and a method for calculating camera parameters are disclosed. The method by which a server calculates camera parameters in order to obtain three-dimensional information, according to various embodiments of the present invention, can comprise the steps of: receiving, from at least two camera devices, image information of dynamic objects moving at a predetermined speed; confirming location information of each dynamic object, included in the image information, on the basis of the same time in each piece of image information received from each camera device; and calculating camera parameters, which indicate the relationship between the camera devices, by using at least a part of each piece of confirmed location information as a corresponding point.

Abstract: Provided are a neurovascular unit (NVU)-on-a-chip and a method of fabricating the same, which 3-dimensionally integrates various human brain cells in a microfluidic platform by using a brain cell co-culture technique so as to simulate a similar environment to the human brain in vitro. The NVU-on-a-chip includes an extracellular matrix (ECM) simulation material (70) in a gel state; and at least one channel (75) which passes through the ECM simulation material (70) and perfuses a culture medium, in which the ECM simulation material (70) contains a plurality of types of human brain cells on an outer side of the channel (75), a brain microvessel endothelial cell lining (91) is formed on an inner side of the channel (75), and the plurality of types of human brain cells and the brain microvessel endothelial cell lining (91) contact each other through the channel (75) to simulate a blood brain barrier (BBB) of a human brain and a neurovascular unit (NVU) of the human brain including the BBB.

Abstract: Provided are a neurovascular unit (NVU)-on-a-chip and a method of fabricating the same, which 3-dimensionally integrates various human brain cells in a microfluidic platform by using a brain cell co-culture technique so as to simulate a similar environment to the human brain in vitro. The NVU-on-a-chip includes an extracellular matrix (ECM) simulation material (70) in a gel state; and at least one channel (75) which passes through the ECM simulation material (70) and perfuses a culture medium, in which the ECM simulation material (70) contains a plurality of types of human brain cells on an outer side of the channel (75), a brain microvessel endothelial cell lining (91) is formed on an inner side of the channel (75), and the plurality of types of human brain cells and the brain microvessel endothelial cell lining (91) contact each other through the channel (75) to simulate a blood brain barrier (BBB) of a human brain and a neurovascular unit (NVU) of the human brain including the BBB.

Abstract: A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the bitline precharge voltage to the output node, and sets the bitline precharge voltage to a target level. The bitline precharge voltage generator generates the bitline precharge voltage having a distribution including the dead zone.

Abstract: A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the bitline precharge voltage to the output node, and sets the bitline precharge voltage to a target level. The bitline precharge voltage generator generates the bitline precharge voltage having a distribution including the dead zone.

Abstract: Provided is a wordline driving circuit and method for a semiconductor memory, in which the wordline driving circuit includes an address decoding signal generator and a wordline voltage supplier. The address decoding signal generator receives a first row address decoding signal (URA) and generates a delayed URA signal (PXID). The wordline voltage supplier has a pull-up transistor for providing the PXID signal to a selected wordline in response to a second row address decoding signal (LRA). The address decoding signal generator sets the PXID signal to a floating state before the selection of the wordline to prevent a leakage current from flowing through the pull-up transistor in a standby mode.

Abstract: A circuit generates a boosted voltage in a semiconductor memory device, where the semiconductor memory device includes a memory cell array having a plurality of non-edge sub-arrays and at least one edge sub-array. The circuit includes a plurality of boosted voltage generators configured to generate a boosted voltage having different current driving capabilities to activate the non-edge sub-arrays and the edge sub-arrays and to supply the boosted voltage to the memory cell array.

Abstract: A semiconductor memory device is disclosed having a layout including, alternating pluralities of memory cell arrays and word line driving blocks arranged next to alternating pluralities of sense amplifier blocks and conjunction blocks, such that each sense amplifier block is located lateral to a corresponding memory cell array, and each conjunction block is located lateral to a corresponding word line driving block. Each sense amplifier block alternately includes one of a supply voltage driver and a ground voltage driver.

Abstract: Provided is a wordline driving circuit and method for a semiconductor memory, in which the wordline driving circuit includes an address decoding signal generator and a wordline voltage supplier. The address decoding signal generator receives a first row address decoding signal (URA) and generates a delayed URA signal (PXID). The wordline voltage supplier has a pull-up transistor for providing the PXID signal to a selected wordline in response to a second row address decoding signal (LRA). The address decoding signal generator sets the PXID signal to a floating state before the selection of the wordline to prevent a leakage current from flowing through the pull-up transistor in a standby mode.

Abstract: A circuit generates a boosted voltage in a semiconductor memory device, where the semiconductor memory device includes a memory cell array having a plurality of non-edge sub-arrays and at least one edge sub-array. The circuit includes a plurality of boosted voltage generators configured to generate a boosted voltage having different current driving capabilities to activate the non-edge sub-arrays and the edge sub-arrays and to supply the boosted voltage to the memory cell array.

Abstract: A semiconductor test circuit is installed inside a semiconductor device to measure the state of at least one electrical signal of the semiconductor device, and includes first, second, and Nth signal selecting units (where N is an integer greater than 2). The first signal selecting unit either outputs a first electrical signal received from a first terminal or provides a high impedance state to a pad connected to a second terminal in response to a first control signal. The second signal selecting unit either outputs a second electrical signal received from a first terminal or provides a high impedance state to the pad connected to a second terminal in response to a second control signal. The Nth signal selecting unit either outputs an Nth electrical signal (N is an integer) received from a first terminal or provides a high impedance state to the pad connected to the second terminal in response to an Nth control signal.

Abstract: A semiconductor memory device is disclosed having a layout including, alternating pluralities of memory cell arrays and word line driving blocks arranged next to alternating pluralities of sense amplifier blocks and conjunction blocks, such that each sense amplifier block is located lateral to a corresponding memory cell array, and each conjunction block is located lateral to a corresponding word line driving block. Each sense amplifier block alternately includes one of a supply voltage driver and a ground voltage driver.

Abstract: A semiconductor test circuit operates without a predetermined delay time and is capable of selecting an electrical signal to be tested even after assembly of a semiconductor device has been completed. The semiconductor test circuit is installed inside the semiconductor device to measure the state of at least one electrical signal of the semiconductor device. The semiconductor test circuit includes first, second, . . . , and Nth signal selecting units (where N is an integer greater than 2). The first signal selecting unit either outputs a first electrical signal received from a first terminal or provides a high impedance state to a pad connected to a second terminal in response to a first control signal. The second signal selecting unit either outputs a second electrical signal received from a first terminal or provides a high impedance state to the pad connected to a second terminal in response to a second control signal.