Abstract: Displaying the images encoded in a display signal which also contains synchronization signals and display enable (DE) signal. The DE signal indicates the time points at which the display data portion of the display signal contains active pixel data elements representing image frames. A display unit generates HDISP and VDISP signals (indicative of the active time in which active pixels and lines are respectively received) based on the DE signal. As the DE signal generally tracks (in the time domain) the active pixel data elements, the active pixel data elements forming image frames are accurately identified, and a superior image quality generally results.

Abstract: A circuit and method for increasing the processing efficiency of texture map data requests within a 3D subunit of a computer controlled graphics display system. The 3D graphics display subsystem includes a polygon engine, a texture map engine and a pixel pipeline. The texture map engine contains a texture map data access (TDA) circuit having a cache controller with a computer readable cache memory for containing recently used texture maps stored in (u,v) coordinate space. The cache controller is limited in handling only n cache miss operations simultaneously. In one embodiment, n is 1. The TDA circuit also contains a texture map address (TMA) FIFO memory unit for storing texture map addresses associated with texture data requests that hit or missed in the cache memory unit. Since the cache controller handles up to n misses, the texture engine stalls when the (n+1).sup.th unprocessed texture request miss is encountered. Therefore, the TMA FIFO at any time contains at most n miss addresses therein.