Patents by Inventor Hongjun Yuan

Hongjun Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7432988
    Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: October 7, 2008
    Assignee: Micronas USA, Inc.
    Inventors: Shuhua Xiang, Hongjun Yuan, Li Sha
  • Patent number: 7359006
    Abstract: A system and method embed an audio signature in a video frame. An audio signature is generated from one bit a buffer input data. Two registers store an audio signature and reference count. According to an embodiment, the audio signature is generated left/right (L/R) interleaved with the left channel data in the most significant bit (MSB).
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: April 15, 2008
    Assignee: Micronas USA, Inc.
    Inventors: Shuhua Xiang, Hongjun Yuan
  • Publication number: 20070153133
    Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.
    Type: Application
    Filed: February 26, 2007
    Publication date: July 5, 2007
    Inventors: Shuhua Xiang, Hongjun Yuan, Sha Li
  • Patent number: 7184101
    Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: February 27, 2007
    Assignee: Micronas USA, Inc.
    Inventors: Shuhua Xiang, Hongjun Yuan, Sha Li
  • Patent number: 7136414
    Abstract: A system and method for efficiently performing an inverse telecine procedure includes an inverse telecine module that converts input frames of video information into corresponding output frames by applying an inverse telecine policy to the input frames. A motion statistics generator then calculates motion statistics results corresponding to the output frames. A synchronizer module then compares the motion statistics results to entries in a synchronization table for determining whether the inverse telecine procedure is correctly synchronized. The synchronizer module may then reposition a current start boundary of the inverse telecine procedure whenever the inverse telecine procedure is not correctly synchronized.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: November 14, 2006
    Assignee: Micronas USA, Inc.
    Inventors: Hongjun Yuan, Sheng Qu, Daniel W. Meyer
  • Publication number: 20060126726
    Abstract: In one embodiment, a DSP structure includes four main sections: DEQ, IDCT for row, IDCT for column, and motion compensation. The data input sequence is organized in such a way to facilitate the data loading into hardware structures for row IDCT and column IDCT. Two types of decoding flows are enabled by the DSP structure: H.264 decoding flows (e.g., dequantization, inverse discrete Hadamard transform, intra prediction, and motion decompensation), and non-H.264 decoding flows (e.g., dequantization, row inverse discrete cosine transformation, column inverse discrete cosine transformation, and motion decompensation). The non-H.264 decoding flow can be used for standards such as MPEG1/2/4, H.263, Microsoft WMV9, and Sony Digital Video.
    Type: Application
    Filed: May 25, 2005
    Publication date: June 15, 2006
    Inventors: Teng Lin, Hongjun Yuan, Weimin Zeng, Liang Peng
  • Publication number: 20060129729
    Abstract: A novel architecture for implementing video processing features a data bus and a control bus. In an embodiment, data transfers between processing modules can take place over the data bus as mediated by a programmable memory copy controller, or through local connections, freeing up the control bus for instructions provided by a processor. A video decoder may be implemented in a system on chip with instructions provided by an off-chip processor. A semaphore or semaphore array mechanism may be used to mediate traffic between the various modules.
    Type: Application
    Filed: July 21, 2005
    Publication date: June 15, 2006
    Inventors: Hongjun Yuan, Shuhua Xiang, Li-Sha Alpha
  • Patent number: 6996702
    Abstract: A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: February 7, 2006
    Assignee: WIS Technologies, Inc.
    Inventors: Shuhua Xiang, Li Sha, Ping Zhu, Hongjun Yuan, Wei Ni
  • Publication number: 20050228970
    Abstract: A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.
    Type: Application
    Filed: July 30, 2002
    Publication date: October 13, 2005
    Inventors: Shuhua Xiang, Li Sha, Ping Zhu, Hongjun Yuan, Wei Ni
  • Publication number: 20050078176
    Abstract: A system and method for efficiently performing an inverse telecine procedure includes an inverse telecine module that converts input frames of video information into corresponding output frames by applying an inverse telecine policy to the input frames. A motion statistics generator then calculates motion statistics results corresponding to the output frames. A synchronizer module then compares the motion statistics results to entries in a synchronization table for determining whether the inverse telecine procedure is correctly synchronized. The synchronizer module may then reposition a current start boundary of the inverse telecine procedure whenever the inverse telecine procedure is not correctly synchronized.
    Type: Application
    Filed: September 15, 2004
    Publication date: April 14, 2005
    Inventors: Hongjun Yuan, Sheng Qu, Daniel Meyer
  • Publication number: 20030025839
    Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.
    Type: Application
    Filed: July 25, 2002
    Publication date: February 6, 2003
    Inventors: Shuhua Xiang, Hongjun Yuan, Sha Li