Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.

Abstract: A system and method embed an audio signature in a video frame. An audio signature is generated from one bit a buffer input data. Two registers store an audio signature and reference count. According to an embodiment, the audio signature is generated left/right (L/R) interleaved with the left channel data in the most significant bit (MSB).

Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.

Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.

Abstract: A system and method for efficiently performing an inverse telecine procedure includes an inverse telecine module that converts input frames of video information into corresponding output frames by applying an inverse telecine policy to the input frames. A motion statistics generator then calculates motion statistics results corresponding to the output frames. A synchronizer module then compares the motion statistics results to entries in a synchronization table for determining whether the inverse telecine procedure is correctly synchronized. The synchronizer module may then reposition a current start boundary of the inverse telecine procedure whenever the inverse telecine procedure is not correctly synchronized.

Abstract: In one embodiment, a DSP structure includes four main sections: DEQ, IDCT for row, IDCT for column, and motion compensation. The data input sequence is organized in such a way to facilitate the data loading into hardware structures for row IDCT and column IDCT. Two types of decoding flows are enabled by the DSP structure: H.264 decoding flows (e.g., dequantization, inverse discrete Hadamard transform, intra prediction, and motion decompensation), and non-H.264 decoding flows (e.g., dequantization, row inverse discrete cosine transformation, column inverse discrete cosine transformation, and motion decompensation). The non-H.264 decoding flow can be used for standards such as MPEG1/2/4, H.263, Microsoft WMV9, and Sony Digital Video.

Abstract: A novel architecture for implementing video processing features a data bus and a control bus. In an embodiment, data transfers between processing modules can take place over the data bus as mediated by a programmable memory copy controller, or through local connections, freeing up the control bus for instructions provided by a processor. A video decoder may be implemented in a system on chip with instructions provided by an off-chip processor. A semaphore or semaphore array mechanism may be used to mediate traffic between the various modules.

Abstract: A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.

Abstract: A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.

Abstract: A system and method for efficiently performing an inverse telecine procedure includes an inverse telecine module that converts input frames of video information into corresponding output frames by applying an inverse telecine policy to the input frames. A motion statistics generator then calculates motion statistics results corresponding to the output frames. A synchronizer module then compares the motion statistics results to entries in a synchronization table for determining whether the inverse telecine procedure is correctly synchronized. The synchronizer module may then reposition a current start boundary of the inverse telecine procedure whenever the inverse telecine procedure is not correctly synchronized.

Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.