Patents by Inventor Honglin Sun
Honglin Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11946334Abstract: A flow splitting device for gas reverse circulation drilling, including: an upper joint for connecting with a double-wall drill pipe; an inner tube which is arranged in the upper joint and defines a first passageway in communication with an inner chamber of the double-wall drill pipe, a second passageway in communication with an annular space in the double-wall drill pipe formed between the inner tube and the upper joint; a lower joint, having an upper end fixedly connected with the upper joint and a lower end for connecting with a drill tool; and a flow guiding member provided between the upper joint and the lower joint. A flexible sealing mechanism is provided outside the upper joint. The flexible sealing mechanism extends radially outward relative to the upper joint and the lower joint to form a sealing contact with a wellbore wall.Type: GrantFiled: September 30, 2020Date of Patent: April 2, 2024Assignees: CHINA PETROLEUM & CHEMICAL CORPORATION, SINOPEC PETROLEUM ENGINEERING TECHNOLOGY SERVICE CO., LTD, SINOPEC SHENGLI PETROLEUM ENGINEERING CO., LTD, DRILLING TECHNOLOGY RESEARCH INSTITUTE OF SINOPEC SHENGLI PETROLEUM ENGINEERING CO., LTDInventors: Chuanwei Zhao, Zhonghua Wu, Yanjun Zhou, Honglin Tang, Zhihe Liu, Xueliang Pei, Haoyu Sun, Zhenguo Su, Bo Kang, Hui Zhang, Huangang Zhu, Yongming Chen, Zhongshuai Chen
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Patent number: 11893283Abstract: Apparatuses and methods can be related to generating an asynchronous process topology in a memory device. The topology can be generated based on the results of a number of processes. The processes can be asynchronous given that the processing resources that implement the processes do not use a clock signal to generate the topology.Type: GrantFiled: June 27, 2022Date of Patent: February 6, 2024Assignee: Micron Technology, Inc.Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
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Patent number: 11854311Abstract: Systems, apparatuses, and methods related to comparison of biometric identifiers in memory are described. An example apparatus includes an array of memory cells, a plurality of logic blocks in complementary metal-oxide-semiconductor (CMOS) under the array, and a controller coupled to the array of memory cells. The controller is configured to control a first portion of the plurality of logic blocks to receive a first subset of a set of biometric identifiers from the array and to perform a first comparison operation thereon and control a second portion of the logic blocks to receive a second subset of the set of biometric identifiers from the array and to perform a second comparison operation thereon. The first and second subsets of the biometric identifiers are different biometric identifiers and the first and second comparison operations are performed to determine a match of the first and second subsets respectively to a stored template.Type: GrantFiled: December 1, 2022Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Honglin Sun, Glen E. Hush, Richard C. Murphy
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Patent number: 11783872Abstract: Systems, apparatuses, and methods related to performing operations within a memory device are described. Such operations may be performed using data latched in multiple sense amplifiers that are distributed among a plurality of sense amplifiers of the memory device. For example, those sense amplifiers, among the plurality of sense amplifiers, storing data associated with the operation(s) can be determined, and the data can be selectively sent from the determined sense amplifiers to an operation unit, in which the operations are performed. The operations may be made without affecting a subsequent read command that requests data from the plurality of sense amplifiers.Type: GrantFiled: December 17, 2021Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: Glen E. Hush, Honglin Sun, Richard C. Murphy
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Patent number: 11762577Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.Type: GrantFiled: September 16, 2022Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
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Patent number: 11749318Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.Type: GrantFiled: August 15, 2022Date of Patent: September 5, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
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Patent number: 11694065Abstract: Devices and methods related to spiking neural units in memory. One device includes a memory array and a complementary metal-oxide semiconductor (CMOS) coupled to the memory array and located under the memory array, wherein the CMOS includes a spiking neural unit comprising logic configured to receive an input to increase a weight stored in a memory cell of the memory array, collect the weight from the memory cell of the memory array, accumulate the weight with an increase based on the input, compare the accumulated weight to a threshold weight, and provide an output in response to the accumulated weight being greater than the threshold weight.Type: GrantFiled: August 28, 2019Date of Patent: July 4, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
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Patent number: 11681797Abstract: Apparatuses and methods can be related to preventing the activation of rows using fuses in, for example, a memory device or a computing system that includes a memory device. The preventing the activation of rows adjacent to a predefined row address range can reduce the charge leakage from the memory cells comprising the predefined row address range. Reducing the charge leakage from memory cells comprising the predefined row address range can increase stability in data retention.Type: GrantFiled: August 28, 2019Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
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Patent number: 11662950Abstract: The present disclosure is related to performing speculation in, for example, a memory device or a computing system that includes a memory device. Speculation can be used to identify data that is accessed together or to predict data that will be accessed with greater frequency. The identified data can be organized to improve efficiency in providing access to the data.Type: GrantFiled: October 14, 2021Date of Patent: May 30, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
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Patent number: 11657009Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing transceivers, receivers, and/or transmitters of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.Type: GrantFiled: September 23, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
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Publication number: 20230111878Abstract: Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator to increase the efficiency of the host and/or accelerator.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Inventors: Honglin Sun, Richard C. Murphy, Glen E. Hush
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Publication number: 20230103659Abstract: Systems, apparatuses, and methods related to comparison of biometric identifiers in memory are described. An example apparatus includes an array of memory cells, a plurality of logic blocks in complementary metal-oxide-semiconductor (CMOS) under the array, and a controller coupled to the array of memory cells. The controller is configured to control a first portion of the plurality of logic blocks to receive a first subset of a set of biometric identifiers from the array and to perform a first comparison operation thereon and control a second portion of the logic blocks to receive a second subset of the set of biometric identifiers from the array and to perform a second comparison operation thereon. The first and second subsets of the biometric identifiers are different biometric identifiers and the first and second comparison operations are performed to determine a match of the first and second subsets respectively to a stored template.Type: ApplicationFiled: December 1, 2022Publication date: April 6, 2023Inventors: Honglin Sun, Glen E. Hush, Richard C. Murphy
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Patent number: 11593002Abstract: Systems, apparatuses, and methods related to multiple artificial neural networks (ANNs) in memory. Such ANNs can be implemented within a memory system (including a number of memory devices) at different granularities. For example, multiple ANNs can be implemented within a single memory device and/or a single ANN can be implemented over multiple memory devices (such that multiple memory devices are configured as a single ANN). The memory system having multiple ANNs can operate each ANN independently from each other such that multiple ANN operations can be concurrently performed.Type: GrantFiled: May 11, 2021Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
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Publication number: 20230020912Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.Type: ApplicationFiled: September 16, 2022Publication date: January 19, 2023Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
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Patent number: 11556759Abstract: Systems, apparatuses, and methods related to comparison of biometric identifiers in memory are described. An example apparatus includes an array of memory cells, a plurality of logic blocks in complementary metal-oxide-semiconductor (CMOS) under the array, and a controller coupled to the array of memory cells. The controller is configured to control a first portion of the plurality of logic blocks to receive a first subset of a set of biometric identifiers from the array and to perform a first comparison operation thereon and control a second portion of the logic blocks to receive a second subset of the set of biometric identifiers from the array and to perform a second comparison operation thereon. The first and second subsets of the biometric identifiers are different biometric identifiers and the first and second comparison operations are performed to determine a match of the first and second subsets respectively to a stored template.Type: GrantFiled: August 6, 2019Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Honglin Sun, Glen E. Hush, Richard C. Murphy
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Patent number: 11526289Abstract: Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator.Type: GrantFiled: July 1, 2021Date of Patent: December 13, 2022Assignee: Micron Technology, Inc.Inventors: Honglin Sun, Richard C. Murphy, Glen E. Hush
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Publication number: 20220392499Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.Type: ApplicationFiled: August 15, 2022Publication date: December 8, 2022Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun
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Publication number: 20220326889Abstract: Apparatuses and methods can be related to generating an asynchronous process topology in a memory device. The topology can be generated based on the results of a number of processes. The processes can be asynchronous given that the processing resources that implement the processes do not use a clock signal to generate the topology.Type: ApplicationFiled: June 27, 2022Publication date: October 13, 2022Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
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Patent number: 11449269Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.Type: GrantFiled: July 22, 2020Date of Patent: September 20, 2022Assignee: Micron Technology, Inc.Inventors: Glen E. Hush, Richard C. Murphy, Honglin Sun
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Publication number: 20220284932Abstract: Apparatuses and methods can be related to implementing a conditional write back scheme for memory. The data may be stored by memory cells of a memory array. The data may be moved to sense circuitry. The data can be conditionally held by the sense circuitry while a plurality of operations is performed. The results of the plurality of operations can dictate whether to commit the data to the memory cells.Type: ApplicationFiled: May 26, 2022Publication date: September 8, 2022Inventors: Richard C. Murphy, Glen E. Hush, Honglin Sun