Abstract: A package substrate, an apparatus for testing power supply noise, and a method for testing power supply noise are provided. The package substrate includes multiple pad arrays, and each of the multiple pad arrays at least includes power supply pads. Power supply pads belonging to a same power supply type in the multiple pad arrays are divided into a test pad and a power supply pad set. The power supply pad set includes power supply pads, other than the test pad, among the power supply pads belonging to the same power supply type, all the power supply pads in the power supply pad set are electrically connected together, and the test pad is configured to perform noise testing of at least one internal power supply corresponding to the same power supply type in a chip to be tested.

Abstract: A semiconductor stack structure at least includes: a substrate; connection pads located on a surface of the substrate; and a plurality of semiconductor dies located on the surface of the substrate and stacked in sequence in a first direction, the first direction being a thickness direction of the substrate. Each two adjacent semiconductor dies located in a same signal channel are connected to a same connection pad, and two semiconductor dies connected to a same connection pad are respectively located in a first channel region and a second channel region of a signal channel.

Abstract: A package substrate, an apparatus for testing power supply noise, and a method for testing power supply noise are provided. The package substrate includes multiple pad arrays, and each of the multiple pad arrays at least includes power supply pads. Power supply pads belonging to a same power supply type in the multiple pad arrays are divided into a test pad and a power supply pad set. The power supply pad set includes power supply pads, other than the test pad, among the power supply pads belonging to the same power supply type, all the power supply pads in the power supply pad set are electrically connected together, and the test pad is configured to perform noise testing of at least one internal power supply corresponding to the same power supply type in a chip to be tested.

Abstract: A test board for testing a memory signal includes a first surface and a second surface. The first surface of the test board comprises a convex region and a non-convex region. The convex region is provided with a first connection area connectable to a main board, and a level at which the convex region is located is higher than a level at which the non-convex region is located by a preset value. The second surface of the test board includes a test area and a second connection area connectable to a memory chip. The test board is provided with a first connection harness for connecting the test area to the first connection area and a second connection harness for connecting the test area to the second connection area, to enable the memory signal of the memory chip to be tested based on the test area.