Abstract: Aspects of a storage device are provided that requests L2P address translation data from an HMB for execution of an associated host command using a dynamically determined HMB transfer size. The storage device includes a volatile memory and a controller. The controller allocates, in the volatile memory, multiple memory locations for L2P address translation data from an HMB. The controller receives a command indicating a host data length, and transmits a request for a portion of the L2P address translation data stored in the HMB for the command. The HMB transfer size associated with the request may be based on the host data length of the associated host command, a quantity of free and contiguous memory locations available in the HMB read buffer, or a minimum between a size of the portion and a total size of the free and contiguous memory locations. Thus, HMB transfer latency may be reduced.

Abstract: Aspects of a storage device including a memory and a controller are provided. In certain aspects, the controller may determine that data stored on a first block satisfies a threshold data-error condition, the data comprising invalid data and valid data. For example, the first block may have a high ratio of valid data to invalid data that satisfies or exceeds a threshold value. In certain aspects, the controller may determine a close block boundary associated with the first block, wherein the close block boundary is configured to bifurcate the first block into a first portion and a second portion, wherein the first portion comprises the data. For example, the controller may determine a boundary defined by a data length, an indirection mapping unit, a physical program boundary, etc.

Abstract: A non-volatile memory device includes a volatile memory, a non-volatile memory, and a controller. The controller is configured to map logical addresses for stored data to physical addresses of the stored data in the non-volatile memory using a logical-to-physical mapping structure stored partially in the volatile memory and at least partially in the non-volatile memory. The controller is configured to perform a storage capacity recovery operation for a region of the non-volatile memory that is selected based at least partially on a number of mappings for the region likely to be stored in the volatile memory for the storage capacity recovery operation.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The data storage device supports zoned namespace. The controller is configured to maintain a zone timestamp table that includes a corresponding timestamp for each zone and add a timestamp to each garbage collection block of the memory device. The controller is further configured to scan a garbage collection block from a last physical block address (PBA) entry to a first PBA entry, determine a zone timestamp for the scanned PBA entry, and compare the zone timestamp to a timestamp of the garbage collection block. The controller is further configured to create and maintain a zone timestamp table and create and maintain a zone based defragmentation table.

Abstract: Systems, methods and computer-readable memory for garbage collection in a storage device. One method comprises, upon a write of data to a first garbage collection unit (GCU) of the storage device, incrementing a number of logical mapping units stored in the first GCU along with a number of logical mapping units with valid data stored in the first GCU. A number of logical mapping units with invalid data stored in a second GCU is decremented based on the incremented number of logical mapping units with valid data stored in the first GCU. The second GCU is erased when a valid data rate of the second GCU is below a valid data rate of the first GCU.

Abstract: Aspects of a storage device including a memory and a controller are provided which allows for reduced latency of read-modify-write operations when a data length from a host is unaligned at two ends with a write length of the controller. When the controller receives from a host device a write command for data, the controller performs a first read of a head portion and a second read of a tail portion immediately after performing the first read. The controller performs a single L2P translation of one of the head or tail portions, senses the data associated with the head and tail portions once into latches, and reads the data from the latches for both the head and tail portions without performing another data sense. The controller then writes the data in response to the write command after performing the first read and the second read.

Abstract: A non-volatile memory device includes a volatile memory, a non-volatile memory, and a controller. The controller is configured to map logical addresses for stored data to physical addresses of the stored data in the non-volatile memory using a logical-to-physical mapping structure stored partially in the volatile memory and at least partially in the non-volatile memory. The controller is configured to perform a storage capacity recovery operation for a region of the non-volatile memory that is selected based at least partially on a number of mappings for the region likely to be stored in the volatile memory for the storage capacity recovery operation.

Abstract: Aspects of a storage device including a memory and a controller are provided which allows for reduced latency of read-modify-write operations when a data length from a host is unaligned at two ends with a write length of the controller. When the controller receives from a host device a write command for data, the controller performs a first read of a head portion and a second read of a tail portion immediately after performing the first read. The controller performs a single L2P translation of one of the head or tail portions, senses the data associated with the head and tail portions once into latches, and reads the data from the latches for both the head and tail portions without performing another data sense. The controller then writes the data in response to the write command after performing the first read and the second read.

Abstract: A device may include a SSD having multiple storage units and a deduplication control circuit configured to determine whether selected data content to be stored is a duplicate of previous data content already in a first buffer of data buffered to be stored in a set of storage units. The deduplication circuit may be further configured to, based on a determination that the selected data content is a duplicate of first previous data content already buffered in the first buffer, instead of buffering another copy of the selected data content, buffer a first header including a first pointer that associates the first header with the first previous data content already buffered in the first buffer. The deduplication circuit may also be configured to reorder the first buffer such that individual data contents in the first buffer are grouped near headers associated with the individual data contents.

Abstract: Methods, apparatuses, and computer-readable media for compressing data for storage or transmission. Input data is compressed in a first stage utilizing a first compression algorithm and the frequencies of occurrence of symbols and symbol pairs in the output from the first stage is calculated. The output from the first stage is then encoded to a final compressed bit string in a second stage utilizing a second compression algorithm based on the calculated frequencies of occurrence of the symbols and the symbol pairs.

Abstract: Systems, methods and computer-readable memory for garbage collection in a storage device. One method comprises, upon a write of data to a first garbage collection unit (GCU) of the storage device, incrementing a number of logical mapping units stored in the first GCU along with a number of logical mapping units with valid data stored in the first GCU. A number of logical mapping units with invalid data stored in a second GCU is decremented based on the incremented number of logical mapping units with valid data stored in the first GCU. The second GCU is erased when a valid data rate of the second GCU is below a valid data rate of the first GCU.

Abstract: Data compression techniques are provided that remove redundancy across the boundary of compression search engines. An illustrative method comprises splitting the data frame into a plurality of sub-chunks; comparing at least two of the plurality of sub-chunks to one another to remove at least one sub-chunk from the plurality of sub-chunks that substantially matches at least one other sub-chunk to generate a remaining plurality of sub-chunks; generating matching sub-chunk information for data reconstruction identifying the at least one removed sub-chunk and the corresponding substantially matched at least one other sub-chunk; grouping the remaining plurality of sub-chunks into sub-units; removing substantially repeated patterns within the sub-units to generate corresponding compressed sub-units; and combining the compressed sub-units with the matching sub-chunk information to generate a compressed data frame.

Abstract: A method operable with a storage system comprises processing an Input/Output (I/O) request to a storage device, extracting a logical mapping unit from the I/O request, determining that the I/O request is for variable length data, and accessing a map that links the logical mapping unit to one or more physical addresses of the storage device. The method also comprises calculating a number of physical mapping units at the physical addresses to service the I/O request.

Abstract: A device may include a SSD having multiple storage units and a deduplication control circuit configured to determine whether selected data content to be stored is a duplicate of previous data content already in a first buffer of data buffered to be stored in a set of storage units. The deduplication circuit may be further configured to, based on a determination that the selected data content is a duplicate of first previous data content already buffered in the first buffer, instead of buffering another copy of the selected data content, buffer a first header including a first pointer that associates the first header with the first previous data content already buffered in the first buffer. The deduplication circuit may also be configured to reorder the first buffer such that individual data contents in the first buffer are grouped near headers associated with the individual data contents.

Abstract: A data storage device includes at least one data storage medium and a controller that is operably coupled to the at least one data storage medium. The controller receives the bit stream in a data storage device and performs a first level of compression on the received bit stream to obtain a symbol frame including a plurality of symbols. The controller encodes an initial portion of the plurality of symbols contained in the symbol frame by a fixed encoding scheme. The controller also collects statistics for the initial portion of the symbol frame. The controller then selects at least one data compression algorithm based on the collected statistics. The controller then performs compression encoding on a remaining portion of the symbol frame with the selected at least one data compression algorithm.

Abstract: Data compression techniques are provided that remove redundancy across the boundary of compression search engines. An illustrative method comprises splitting the data frame into a plurality of sub-chunks; comparing at least two of the plurality of sub-chunks to one another to remove at least one sub-chunk from the plurality of sub-chunks that substantially matches at least one other sub-chunk to generate a remaining plurality of sub-chunks; generating matching sub-chunk information for data reconstruction identifying the at least one removed sub-chunk and the corresponding substantially matched at least one other sub-chunk; grouping the remaining plurality of sub-chunks into sub-units; removing substantially repeated patterns within the sub-units to generate corresponding compressed sub-units; and combining the compressed sub-units with the matching sub-chunk information to generate a compressed data frame.

Abstract: A data storage device includes at least one data storage medium and a controller that is operably coupled to the at least one data storage medium. The controller receives the bit stream in a data storage device and performs a first level of compression on the received bit stream to obtain a symbol frame including a plurality of symbols. The controller encodes an initial portion of the plurality of symbols contained in the symbol frame by a fixed encoding scheme. The controller also collects statistics for the initial portion of the symbol frame. The controller then selects at least one data compression algorithm based on the collected statistics. The controller then performs compression encoding on a remaining portion of the symbol frame with the selected at least one data compression algorithm.