Abstract: The present invention discloses the synthesis of a novel crosslinker having the following structure: R1 is C(R8) (R9) wherein (R8) is H, or an alkyl group having 1-5 carbon atoms, and (R9) is H, or an alkyl group having 1-5 carbon atoms. R2 is H, or an alkyl group having 1-5 carbon atoms. R3 is H or an alkyl group having 1-5 carbon atoms. R4 is an alkyl group having 1-5 carbon atoms. R5 is H or an alkyl group having 1-5 carbon atoms. R6 is H or an alkyl group having 1-5 carbon atoms. R7 is C(R10) (R11) wherein (R10) is H, or an alkyl group having 1-5 carbon atoms, and (R11) is H, or an alkyl group having 1-5 carbon atoms. The crosslinker is stable in a basic environment, but decomposable in an acidic environment.

Abstract: An approximate reasoning apparatus converts input data into a degree of membership by a membership function, obtains an information quantity for each of a number of factors using the degree of membership, and obtains the possibility of a conclusion using the degree of membership and the information quantities. As a result, the accuracy of an information quantity which prevails at the moment data is entered is taken into consideration to obtain results of reasoning having a high identification capability. Further, a static information quantity of each factor is calculated, the clarity of each factor is obtained from the static information quantity, the clarity of a factor for which data has been entered is calculated from the clarity of each factor, and the finally calculated clarity is displayed as clarity regarding results of reasoning. This makes it possible to judge the reliability of the results of reasoning from the displayed clarity.

Abstract: A fuzzy inference system and its method of operation. The system comprises an inference unit (30) of pipeline architecture, a control unit (20) for controlling the operation of the inference unit, and a host computer (10) for supervising the entire operation. A plurality of inference rule groups (referred to as rule cells) each for controlling an object to be controlled are stored in a rule memory (22) of the control unit (20). The rule cell is composed of a number of path codes. The path code includes object data to be processed and operation codes. The operation codes are to control each of processing/operation sections (31 to 35) of the inference unit (30).

Abstract: A truth-valued-flow processing unit according to the invention comprises truth value generator circuits truth-valued-flow inference units a truth value converter, a first bus and a second bus. The first bus is provided in a number equal to the number of kinds of input variables. The second bus comprises a number of lines equal to the number of kinds of a plurality of predetermined functions used by the consequents of implications. The truth value generator circuit is provided in a number equal to the number of kinds of input variables. Each truth value generator circuit is connected at an output side thereof to a corresponding one of the first buses, generates truth values and outputs the truth values on the corresponding first bus.

Abstract: A truth-valued-flow inference unit according to the invention is for outputting truth values representing inferential results regarding a plurality of antecedents for which consequents in implications are the same. The inference unit includes a selector circuit (18, 71-74, 81-84, 91-94, 75, 76, 85, 86, 95, 96) for selectively outputting, for each of a plurality of antecedents in accordance with set rules and with regard to each of a plurality of kinds of input variables, truth values inputted thereto in correspondence with respective ones of the input variables with regard to a plurality kinds of predetermined functions used by the antecedents, and an operation circuit (19, 77-80, 90) for performing an operation between the truth values outputted by the selector circuit and all input variables for each antecedent, and further for performing a unifying operation on the results of this operation.

Abstract: A truth value generating basic circuit according to the invention is characterized by having one or a plurality of basic function generator circuits (23, 24) which receive an analog applied input and include an operational amplifier (A.sub.1), and an operation circuit (21, 22). The operation circuit (21, 22) performs a prescribed operation upon receiving, as inputs thereto, an output signal representing a basic function of each basic function generator circuit, and signals corresponding to grades 0 and 1. Alternative embodiments of the truth value generating circuit include and A/D converter (39) for converting an analog input into digital access data which are applied to digital memory (31-34). A truth value generating circuit (TG, TG1-TG3) according to the invention is constituted by providing a plurality of the truth value generating basic circuits, with a different membership function being set in each truth value generating basic circuit.

Abstract: A truth value generator circuit array (11) includes truth value generator circuits (TG1-TG3) the number of which is the same as the number of kinds of input variables. Each truth value generator circuit generates truth values, which correspond to an applied input variable, with regard to a plurality of predetermined functions used by the antecedent of implications. The truth-valued-flow inference unit array includes truth-value-flow inference units (TVFI1-TVFI7) the number of which is the same as the number of predetermined functions used by the consequent of implications. Each truth-valued-flow inference unit corresponds to each function used by the consequent. All truth values outputted by the truth value generator circuit array enter each of the truth-valued-flow inference units. Each truth-valued-flow inference unit selects input truth values in accordance with predetermined rules and subjects these truth values to a prescribed operation.

Abstract: A truth value converter in which a memory stores, for every consequent, a weighted coefficient, which represents a function of a consequent of an implication by a singleton, a first arithmetic processor for taking the products of input truth values that are to act upon consequents and weighted coefficients in the memory corresponding to these input truth values, and further for taking the sum of these products, a second arithmetic processor for taking the sum of a plurality of the input truth values, and a third arithmetic processor for dividing an output of the first arithmetic processor by an output of the second arithmetic processor. The inferential results of each rule are given as truth values and the functions of the consequents on which the truth values are to act are expressed by singletons. This simplifies combining processing and defuzzification as well as the circuit arrangment.