Abstract: A variable frequency oscillator (VFO) circuit having an increased frequency tuning range to selectively obtain operating frequencies above and below a set frequency. The circuit includes a tank inductor connected in parallel with a tank capacitor for primarily defining the set oscillating frequency of the VFO circuit. A switchable capacitor is included for selectively providing a predetermined step-wise decrease of the oscillating frequency to a frequency value below the set frequency of the circuit, and a varactor is included for accommodating selective tuning of the oscillating frequency within a range of frequency values below the set frequency. The inventive circuit selectively includes a switchable inductance element which is selectively electromagnetically coupled to the tank inductor to decrease the overall inductance value of the VFO circuit and, thereby, selectively increase the oscillating frequency above the set frequency value.

Abstract: An oscillator circuit for increasing the signal power of a generated oscillating signal while decreasing phase noise. The circuit includes an oscillating stage having an inductor and capacitors for producing a periodic oscillating signal and a first control signal. An active stage having a transistor with a gate terminal, a source terminal and a drain terminal is connected to the oscillating stage so that the first control signal is provided to the source terminal of the transistor. A second control signal is provided to the transistor gate terminal for increasing the voltage applied to the gate terminal when the first control signal decreases the voltage applied to the source terminal, thus controlling the activation of the transistor for supplying signal boosting power to the tank stage.

Abstract: A high frequency divider circuit for producing output signals of half the frequency of an input clock signal includes two identical circuit sections, each producing an output signal and its complement. The circuit sections are connected to each other so that the output signals of one circuit section serve as input signals to the other circuit section. Each circuit section contains a load transistor which is controlled by one of the clock signal and the clock signal complement, and a switch transistor which is controlled by the other of the clock signal and the clock signal complement. The inventive circuit exhibits a reduced RC time constant for each circuit section and an increased output signal swing between the output signals and their respective complements, as contrasted with prior art frequency dividers, thereby increasing the overall circuit response time and its ability to operate at high frequencies.

Abstract: A frequency divider circuit operable at high frequencies for producing an output signal having a frequency value equal to substantially half the frequency value of a clock signal from which the circuit operates. The circuit includes a first transistor branch, an inventor and a second transistor branch. The first transistor branch is connected to an input of the inventor and the second transistor branch is connected to an output of the inventor. The first transistor branch receives a plurality of input signals including the clock signal, a compliment of the clock signal, and the circuit output signal and produces an input signal which is provided to the inventor. The second transistor branch receives a plurality of inputs including the compliment of the clock signal, the clock signal and the inventor output signal, and produces the circuit output signal. The circuit is configured such that the next inventor state is always available for conveyance to the output signal upon a change in the clock signal.

Abstract: A switched power amplifier circuit employs non-linear amplifier stages including MOSFET transistors. The transistors each have source, gate, drain and backgate terminals. An input Rf signal is applied to the gate terminals and the source (or drain) terminals are connected to a load. The transistors are operated as switches by selectively applying clock signals to the backgate terminals to activate desired transistors, thus causing the transistors to turn on and allow current to flow through the load to generate power. The power to the load is increased by turning on multiple transistors at any given time.

Abstract: A differential amplifier for amplifying the difference between first and second input signals and producing therefrom a differential output signal. The differential amplifier includes first and second transistors connected to a common DC current source and receiving, at the transistor gate terminals, the respective first and second input signals. Each transistor has a common mode voltage associated therewith. A voltage control circuit generates control signals that are applied to the backgate terminals of the transistors to calibrate the differential output voltage and to adjust the common mode voltages of the transistors.

Abstract: A circuit for receiving an input signal having a phase component and an amplitude component which carry information, and for producing an output driver signal containing the phase and amplitude component information for driving a non-linear amplifier for generating linear amplification. The circuit includes a voltage controlled oscillator for receiving the phase component and for outputting a phase modulated carrier signal having a duty cycle and a constant amplitude. A driver stage made from a plurality of invertors, each having a pair of MOSFET transistors, receives the carrier signal at the gate terminals of the transistors. The amplitude component is used to drive the invertors by applying the amplitude component to the backgate terminals of at least some of the transistors in the invertors to pulse width modulate the carrier signal.

Abstract: A voltage controlled oscillator (VCO) CMOS circuit wherein back gate terminals of CMOS transistors are used to vary the parasitic capacitances of the transistors. The back gate terminals receive a signal from a variable voltage source so that oscillation can be controlled by adjusting the variable voltage. The CMOS transistors are connected across an inductor and the transconductance characteristics of the transistors reduce the resistance of the inductor, thereby improving circuit oscillation and providing enhanced stability and capabilities at high operating frequencies.

Abstract: A four terminal multiplication circuit capable of mixing up to three input signals. The circuit includes a MOS transistor having gate, source, drain and back-gate terminals. When the circuit is used as an RF mixer or downconverter, an RF signal is provided to the gate terminal and a local oscillator signal is provided to the back-gate terminal. A DC voltage is applied to the source terminal for biasing the transistor and the mixed/downconverted output (IF) signal is obtained from the drain terminal. A single balanced and a double balanced mixer circuit are also disclosed. In the single balanced circuit, two MOS transistors are used; the RF signal is applied to the gate terminals with the positive phase LO component applied to one back-gate terminal and the negative phase local oscillator (LO) component applied to the other back-gate terminal for producing a positive phase and a negative phase IF signal.

Abstract: Disclosed is an integrated circuit comprising a balanced set of inputs and a phase splitting circuit. The phase splitting circuit has a first input terminal that is coupled to the balanced set of inputs and a second input terminal that is coupled to the balanced set of inputs. The phase splitting circuit further comprises a balanced phase shifting network, a first set of output terminals, and a second set of output terminals. The balanced phase shifting network is coupled to the first: input terminal and the second input terminal. The first set of output terminals provides a voltage representative of a first voltage across a resistive portion of the balanced phase shifting network in response to an input voltage at the balanced set of inputs. The second set of output terminals provides a voltage representative of a second voltage across a reactive portion of the balanced phase shifting network in response to the input voltage at the balanced set of inputs.