Abstract: A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.

Abstract: A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.

Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are provided. The thin film transistor is provided on a base substrate and includes: an active layer including a first surface and a second surface which are opposite to each other, in which the second surface is closer to the base substrate than the first surface; and a source-drain electrode layer including a source electrode and a drain electrode which are separated from each other and are respectively connected with the active layer; each of the first surface and the second surface is a non-flat surface, and the non-flat surface includes a plurality of depressions and a plurality of protrusions which are alternately arranged.

Abstract: There is provided a thin film transistor including: a substrate; a gate electrode and a first electrode in a single layer on the substrate; an active layer above the first electrode, an orthographic projection of the active layer on the substrate at least partially covers an orthographic projection of the first electrode on the substrate; a first insulation layer covering the gate electrode, the first electrode, the active layer, a portion of the substrate exposed between the gate electrode and the active layer, and another portion of the substrate exposed between the gate electrode and the first electrode; and a second electrode above the first insulation layer, an orthographic projection of the second electrode on the substrate at least partially covers the orthographic projection of the active layer on the substrate, and the second electrode is connected to the active layer through a via-hole in the first insulation layer.

Abstract: The disclosure discloses a thin film transistor, a method for fabricating the same, an array substrate, and a display panel. The thin film transistor includes: a first conductive layer on a base substrate, a first insulation layer on a side of the first conductive layer facing away from the base substrate, and a second conductive layer on a side of the first insulation layer facing away from the first conductive layer, wherein an active layer is arranged on a side of the first insulation layer facing the first conductive layer, and/or a side thereof facing the second conductive layer.

Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are provided. The thin film transistor is provided on a base substrate and includes: an active layer including a first surface and a second surface which are opposite to each other, in which the second surface is closer to the base substrate than the first surface; and a source-drain electrode layer including a source electrode and a drain electrode which are separated from each other and are respectively connected with the active layer; each of the first surface and the second surface is a non-flat surface, and the non-flat surface includes a plurality of depressions and a plurality of protrusions which are alternately arranged.

Abstract: The disclosure discloses a thin film transistor, a method for fabricating the same, an array substrate, and a display panel. The thin film transistor includes: a first conductive layer on a base substrate, a first insulation layer on a side of the first conductive layer facing away from the base substrate, and a second conductive layer on a side of the first insulation layer facing away from the first conductive layer, wherein an active layer is arranged on a side of the first insulation layer facing the first conductive layer, and/or a side thereof facing the second conductive layer.

Abstract: There is provided a thin film transistor including: a substrate; a gate electrode and a first electrode in a single layer on the substrate; an active layer above the first electrode, an orthographic projection of the active layer on the substrate at least partially covers an orthographic projection of the first electrode on the substrate; a first insulation layer covering the gate electrode, the first electrode, the active layer, a portion of the substrate exposed between the gate electrode and the active layer, and another portion of the substrate exposed between the gate electrode and the first electrode; and a second electrode above the first insulation layer, an orthographic projection of the second electrode on the substrate at least partially covers the orthographic projection of the active layer on the substrate, and the second electrode is connected to the active layer through a via-hole in the first insulation layer.

Abstract: A patterning method employing a half tone mask includes the steps of: successively forming a first thin film layer, a second thin film layer and a photoresist thin film layer on a substrate; exposing and developing the photoresist thin film layer by using a half tone mask plate; performing a first etching on the substrate that is exposed and developed; performing a second etching on the substrate that has been subject to the first etching; passivating the substrate that has been subject to the first etching; ashing the substrate that has been passivated; performing a third etching on the substrate that has been subject to the ashing and the second etching; and, stripping the substrate that has been subject to the third etching.

Abstract: A patterning method employing a half tone mask includes the steps of: successively forming a first thin film layer, a second thin film layer and a photoresist thin film layer on a substrate; exposing and developing the photoresist thin film layer by using a half tone mask plate; performing a first etching on the substrate that is exposed and developed; performing a second etching on the substrate that has been subject to the first etching; passivating the substrate that has been subject to the first etching; ashing the substrate that has been passivated; performing a third etching on the substrate that has been subject to the ashing and the second etching; and, stripping the substrate that has been subject to the third etching.