Abstract: The disclosure discloses a Gm-APD array lidar imaging method under strong background noise, comprising following steps: respectively acquiring two sets of cumulative detection data of the Gm-APD array lidar at two different opening times of a range gate of the Gm-APD array lidar under strong background noise; respectively performing a statistic operation on the two sets of cumulative detection data of the Gm-APD array lidar with respect to all pixels, to obtain two cumulative detection result histograms of the Gm-APD array lidar; determining a range interval of the imaging target according to the two cumulative detection result histograms; and acquiring a lidar image by a peak discrimination method in the range interval of the imaging target. The Gm-APD array lidar imaging method according to the present disclosure is capable of improving the laser image quality by eliminating the interference of strong background noise in other range intervals.

Abstract: The disclosure discloses a Gm-APD array lidar imaging method under strong background noise, comprising following steps: respectively acquiring two sets of cumulative detection data of the Gm-APD array lidar at two different opening times of a range gate of the Gm-APD array lidar under strong background noise; respectively performing a statistic operation on the two sets of cumulative detection data of the Gm-APD array lidar with respect to all pixels, to obtain two cumulative detection result histograms of the Gm-APD array lidar; determining a range interval of the imaging target according to the two cumulative detection result histograms; and acquiring a lidar image by a peak discrimination method in the range interval of the imaging target. The Gm-APD an-ay lidar imaging method according to the present disclosure is capable of improving the laser image quality by eliminating the interference of strong background noise in other range intervals.

Abstract: The invention discloses a method for generating a row transposed architecture based on a two-dimensional FFT processor, comprising the following characteristic: the FFT processor includes an on-chip row transposition memory for storing an image row transposition result. When the size of the row transposition result exceeds the capacity of the on-chip memory, the first 2k data of a row of the two-dimensional array after row transformation is written into the on-chip row transposition memory, the remaining data is written into the off-chip SDRAM, and k is acquired through calculation according to the row transposition result and the capacity of the on-chip row transposition memory. The on-chip memory is divided into two memories A and B used for storing the row transposition partial result and temporarily storing data read from off-chip SDRAM.

Abstract: The invention discloses a method for generating a row transposed architecture based on a two-dimensional FFT processor, comprising the following characteristic: the FFT processor includes an on-chip row transposition memory for storing an image row transposition result. When the size of the row transposition result exceeds the capacity of the on-chip memory, the first 2k data of a row of the two-dimensional array after row transformation is written into the on-chip row transposition memory, the remaining data is written into the off-chip SDRAM, and k is acquired through calculation according to the row transposition result and the capacity of the on-chip row transposition memory. The on-chip memory is divided into two memories A and B used for storing the row transposition partial result and temporarily storing data read from off-chip SDRAM.

Abstract: A radiation-hardened memory storage unit that is resistant to total ionizing done effects, the unit including PMOS transistors.

Abstract: A radiation-hardened storage unit, including a basic storage unit, a redundant storage unit, and a two-way feedback unit. The basic storage unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The first PMOS transistor and the second PMOS transistor are read-out access transistors. The third PMOS transistor and the fourth PMOS transistor are write-in access transistors. The redundant storage unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The fifth PMOS transistor and the sixth PMOS transistor are read-out access transistors. The seventh PMOS transistor and the eighth PMOS transistor are write-in access transistors. The two-way feedback unit is configured to form a feedback path between the storage node and the redundant storage node.

Abstract: A radiation-hardened memory storage unit that is resistant to total ionizing done effects, the unit including PMOS transistors.

Abstract: A radiation-hardened storage unit, including a basic storage unit, a redundant storage unit, and a two-way feedback unit. The basic storage unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The first PMOS transistor and the second PMOS transistor are read-out access transistors. The third PMOS transistor and the fourth PMOS transistor are write-in access transistors. The redundant storage unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor. The fifth PMOS transistor and the sixth PMOS transistor are read-out access transistors. The seventh PMOS transistor and the eighth PMOS transistor are write-in access transistors. The two-way feedback unit is configured to form a feedback path between the storage node and the redundant storage node.