Abstract: Disclosed is an organic light emitting diode (OLED) comprising at least one emitting unit that includes a first compound, which may have a bipolar property, a second compound, which may have a delayed fluorescent property, and a third compound, which may have narrow FWHM (full width at half maximum) and a fluorescent property, and an organic light emitting device including the OLED. Further the compounds have defined relative LUMO and HOMO energies. The OLED and the organic light emitting device has enhanced luminous efficiency, color purity and luminous life span as well as low driving voltage.

Abstract: An organic compound including a carbazolyl moiety having a p-type property, a dibenzofuranyl or dibenzothiophenyl moiety having an n-type property and further substituted with a dibenzofuranyl or dibenzothiophenyl moiety is disclosed. An organic light emitting diode and an organic light emitting device including the organic compound are also disclosed. The organic compound has excellent thermal resistance and a high energy level due to the combination of fused hetero aromatic rings. Therefore, the organic light emitting diode and the organic light emitting device including the organic compound show excellent luminous efficiency and an improved luminous lifetime.

Abstract: Disclosed is an organic light emitting diode (OLED) includes a first emitting material layer, which includes a first compound and a second compound, and a second emitting material layer, which includes a third compound and a fourth compound, wherein a HOMO energy level of the first compound is higher than a HOMO energy level of the second compound and a HOMO energy level of the third compound is lower than a HOMO energy level of the fourth compound, and an organic light emitting device having the OLED. The OLED and the organic light emitting device disclosed have enhanced luminous efficiency, color purity and luminous life span as well as low driving voltage by applying the emitting material layer.

Abstract: An organic compound including a carbazolyl moiety having a p-type property, a dibenzofuranyl or dibenzothiophenyl moiety having an n-type property and further substituted with a dibenzofuranyl or dibenzothiophenyl moiety is disclosed. An organic light emitting diode and an organic light emitting device including the organic compound are also disclosed. The organic compound has excellent thermal resistance and a high energy level due to the combination of fused hetero aromatic rings. Therefore, the organic light emitting diode and the organic light emitting device including the organic compound show excellent luminous efficiency and an improved luminous lifetime.

Abstract: Disclosed is an organic light emitting diode (OLED) includes a first emitting material layer, which includes a first compound and a second compound, and a second emitting material layer, which includes a third compound and a fourth compound, wherein a HOMO energy level of the first compound is higher than a HOMO energy level of the second compound and a HOMO energy level of the third compound is lower than a HOMO energy level of the fourth compound, and an organic light emitting device having the OLED. The OLED and the organic light emitting device disclosed have enhanced luminous efficiency, color purity and luminous life span as well as low driving voltage by applying the emitting material layer.

Abstract: Disclosed is an organic light emitting diode (OLED) comprising at least one emitting unit that includes a first compound, which may have a bipolar property, a second compound, which may have a delayed fluorescent property, and a third compound, which may have narrow FWHM (full width at half maximum) and a fluorescent property, and an organic light emitting device including the OLED. Further the compounds have defined relative LUMO and HOMO energies. The OLED and the organic light emitting device has enhanced luminous efficiency, color purity and luminous life span as well as low driving voltage.

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Abstract: An apparatus for measuring static electricity on a substrate includes a measuring unit, an information processing unit, and a display unit. The measuring unit measures first static electricity information from the substrate. The information processing unit calculates a static electricity distribution state of the substrate using the first static electricity information. The display unit displays a graphic image representing the static electricity distribution state. The information processing unit includes a calculating unit and a controller. The calculating unit estimates second static electricity information using the first static electricity information. The controller calculates the static electricity distribution state of the substrate using the first static electricity information and the second static electricity information.

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Abstract: A semiconductor device includes a substrate, a first region and a second region. Each of the first region and second region includes a trench, an epitaxial layer including a source/drain having a first part and a second part, the first part extending from a top surface of the substrate to a top surface of the source/drain and the second part extending from the top surface of the substrate to a bottom surface of the source/drain in the trench. The cross-sectional shape of the first part of the source/drain of the first region is the same as the cross-sectional shape of the first part of the source/drain of the second region. The cross-sectional shape of the second past of the source/drain of the find region is different from the cross-sectional shape of the second part of the source/drain of the second region.

Abstract: Methods of forming carbon nanotubes include forming a catalytic metal layer on a sidewall of an electrically conductive region, such as a metal or metal nitride pattern. A plurality of carbon nanotubes are grown from the catalytic metal layer. These carbon nanotubes can be grown from a sidewall of the catalytic metal layer. The plurality of carbon nanotubes are then exposed to an organic solvent. This step of exposing the carbon nanotubes to the organic solvent may be preceded by a step of applying centrifugal forces to the plurality of carbon nanotubes. Alternatively, the exposing step may include applying a centrifugal force to the plurality of carbon nanotubes while simultaneously exposing the plurality of carbon nanotubes to an organic solvent.

Abstract: A semiconductor device includes a substrate, a first region and a second region. Each of the first region and second region includes a trench, an epitaxial layer including a source/drain having a first part and a second part, the first part extending from a top surface of the substrate to a top surface of the source/drain and the second part extending from the top surface of the substrate to a bottom surface of the source/drain in the trench. The cross-sectional shape of the first part of the source/drain of the first region is the same as the cross-sectional shape of the first part of the source/drain of the second region. The cross-sectional shape of the second part of the source/drain of the first region is different from the cross-sectional shape of the second part of the source/drain of the second region.

Abstract: A variable resistance memory device includes a variable resistance memory cell, and a by-pass circuit configured to electrically by-pass a programming pulse supplied to the variable resistance memory cell after a resistive state of the variable resistance memory cell has changed in response to the programming pulse.

Abstract: A method of fabricating a semiconductor device and a semiconductor device are provided. The method includes method of fabricating a semiconductor device including providing a semiconductor substrate having a first semiconductor device region and a second semiconductor device region defined therein, forming a first gate structure in the first semiconductor device region, forming a second gate structure in the second semiconductor device region, forming a first trench adjacent to a first side of the first gate structure, forming a second trench adjacent to a first side of the second gate structure, and forming a first semiconductor pattern in the first trench and forming a second semiconductor pattern in the second trench, wherein the first and second trenches have different cross-sectional shapes from each other.

Abstract: Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.

Abstract: Multi-level nonvolatile memory devices using variable resistive elements, the multi-level nonvolatile memory devices including a word line, a bit line, and a multi-level memory cell coupled between the word line and the bit line, the multi-level memory cell having first resistance level and a second resistance level higher than the first resistance level when the first and second write biases having the same polarity are applied thereto, and a third resistance level and a fourth resistance level ranging between the first and second resistance levels, when third and fourth write biases having different polarities from each other are applied thereto.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device may include a local bitline extending in a direction substantially vertical to an upper surface of a semiconductor substrate and a local wordline intersecting the local bitline. The local bitline is electrically connected to a bitline channel pillar penetrating a gate of a bitline transistor, and the local wordline is electrically connected to a wordline channel pillar penetrating a gate of a wordline transistor.