Abstract: Disclosed is a method for stripping a gallium nitride substrate, including: a gallium nitride substrate with a gallium nitride epitaxial structure directly grown on an upper surface thereof is acquired; an interior of the gallium nitride substrate is scanned and irradiated via the epitaxial structure by a laser beam, so as to generate a decomposition layer in the gallium nitride substrate, the laser beam being a laser having a pulse width on the order of less than 10?15 s, and a distance between the decomposition layer and the upper surface of the gallium nitride substrate being less than a thickness of the gallium nitride substrate; and the gallium nitride substrate is separated at the decomposition layer, so as to obtain a stripped gallium nitride substrate and a semiconductor device.

Abstract: A video data processing method, system and apparatus, and a computer readable storage medium are disclosed. The video data processing method includes: when a reading signal is received, determining a storage space where video data to be compressed corresponding to the reading signal is located; in response to a determination that the storage space is a DDR storage space, reading video data of a plurality of Blocks from the DDR storage space, sending the video data to be compressed in the video data to a compression module for compression, and storing video data other than the video data to be compressed into a RAM storage space; and in response to a determination that the storage space is the RAM storage space, reading the video data to be compressed from the RAM storage space, and sending the video data to be compressed to the compression module for compression.

Abstract: Disclosed in the present disclosure are a video compression system and a server. The video compression system includes a Central Processing Unit (CPU), a hardware detection module, a write control module, a read control module, and an First In First Out (FIFO) array module; the CPU is configured to send a first enable signal to the hardware detection module, the read control module, and the selection switch; the selection switch is configured to select to write test data into the FIFO array module through the hardware detection module based on the first enable signal; the hardware detection module is configured to write test data into the FIFO array module based on the first enable signal; and the read control module is configured to read the test data from the FIFO array module based on the first enable signal and transmit the test data to the hardware detection module.

Abstract: A system starting method includes: reading secure startup data; judging whether a private key number in the secure startup data is the same as a public key number recorded in a one time programmable memory, where the one time programmable memory records a currently effective public key number; when the private key number is the same as the public key number, performing a system startup procedure; and when the private key number is different from the public key number, sending a startup ending instruction.

Abstract: Disclosed in the present disclosure are a video compression system and a server. The video compression system includes a Central Processing Unit (CPU), a hardware detection module, a write control module, a read control module, and an First In First Out (FIFO) array module; the CPU is configured to send a first enable signal to the hardware detection module, the read control module, and the selection switch; the selection switch is configured to select to write test data into the FIFO array module through the hardware detection module based on the first enable signal; the hardware detection module is configured to write test data into the FIFO array module based on the first enable signal; and the read control module is configured to read the test data from the FIFO array module based on the first enable signal and transmit the test data to the hardware detection module.

Abstract: The present application discloses method for transmitting video data, applied to chip for substrate management control. The method includes: respectively storing video compression data into first storage space and second storage space according to ping-pong operation structure; reading data of the same byte length from the first storage space and the second storage space; determining whether similarity between first data to be transmitted and second data to be transmitted is greater than or equal to preset value; if yes, setting the first data to be transmitted added with first transmission identifier as the current frame of data, and setting a second transmission identifier corresponding to the first transmission identifier as the next frame of data; and sending the current frame data and the next frame data to video data receiving end.

Abstract: The present application discloses a branch instruction processing method, system, and device, and a computer storage medium. The method includes: determining, on the basis of a target branch instruction, a branch instruction to be predicted (S101); predicting, on the basis of a plurality of preset branch prediction methods, the branch instruction to be predicted, so as to obtain a corresponding prediction result (S102); determining the prediction accuracy of each branch prediction method on the basis of the prediction result (S103); determining the branch prediction method corresponding to the highest prediction accuracy as a target branch prediction method (S104); and performing branch prediction on the target branch instruction on the basis of the target branch prediction method (S105).

Abstract: An electronic device and a memristor-based logic gate circuit thereof. In the present application, a control end of a controllable switch is connected to a negative end of an output memristor in a MAGIC-based AND logic gate, and whether a second memristor is powered on is controlled by the controllable switch. Thus, when resistance value states of two input memristors in the AND logic gate are different, the controllable switch will conduct and power on the second memristor, and the second memristor will present a low-resistance state at this time. When the resistance value states of the two input memristors are the same, the controllable switch will not conduct and the second memristor will then remain the state unchanged, i.e., presents a high-resistance state. An exclusive OR logic gate is formed by combining the two input memristors and the second memristor.

Abstract: Disclosed is a method for stripping a gallium nitride substrate, including: a gallium nitride substrate with a gallium nitride epitaxial structure directly grown on an upper surface thereof is acquired; an interior of the gallium nitride substrate is scanned and irradiated via the epitaxial structure by a laser beam, so as to generate a decomposition layer in the gallium nitride substrate, the laser beam being a laser having a pulse width on the order of less than 10?15 s, and a distance between the decomposition layer and the upper surface of the gallium nitride substrate being less than a thickness of the gallium nitride substrate; and the gallium nitride substrate is separated at the decomposition layer, so as to obtain a stripped gallium nitride substrate and a semiconductor device.

Abstract: Disclosed are a method and apparatus for processing video compression. The method includes: controlling a comparison apparatus to perform frame-wise writing of original video data to an external storage apparatus, and controlling a video compression control component to perform frame-wise reading of the original video data from the external storage apparatus; in response to writing original video data of a non-first frame into the external storage apparatus, and if yes, and in response to writing the original video data of the current frame into the external storage apparatus, converting the video data into tag information and writing the tag information into the external storage apparatus; and in response to reading the original video data of the previous frame from the external storage apparatus, writing the video data corresponding to the current same line number into an internal storage apparatus.

Abstract: A monitoring video compression method, a monitoring system, a computer device, and a medium. The method includes: a monitoring center configuring a key monitoring point and sending configuration information of the key monitoring point to a video server through a management center; the video server receiving the configuration information of the key monitoring point, selecting a corresponding video source based on the configuration information of the key monitoring point, transferring the corresponding video source from a video compression module to a baseboard management controller (BMC) for compression, and writing the corresponding video source into a storage space of the video server after the compression is completed.

Abstract: An electronic device and a memristor-based logic gate circuit thereof. In the present application, a control end of a controllable switch is connected to a negative end of an output memristor in a MAGIC-based AND logic gate, and whether a second memristor is powered on is controlled by the controllable switch. Thus, when resistance value states of two input memristors in the AND logic gate are different, the controllable switch will conduct and power on the second memristor, and the second memristor will present a low-resistance state at this time. When the resistance value states of the two input memristors are the same, the controllable switch will not conduct and the second memristor will then remain the state unchanged, i.e., presents a high-resistance state. An exclusive OR logic gate is formed by combining the two input memristors and the second memristor.

Abstract: Disclosed in the present application is a video data transmission method, which is applied to a substrate management control chip. The video data transmission method comprises: respectively storing compressed video data in a first storage space and a second storage space according to a ping-pong operation structure; reading data of the same byte length from the first storage space and the second storage space; determining whether the similarity between first data to be transmitted and second data to be transmitted is greater than or equal to a preset value; if so, setting, as the current frame of data, said first data to which a first transmission identifier is added, and setting, as the next frame of data, a second transmission identifier corresponding to the first transmission identifier; and sending the current frame of data and the next frame of data to a video data receiving end.

Abstract: The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a Nb2N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb2N sacrificial layer; growing a Ta2N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta2N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb2N sacrificial layer and the Ta2N sacrificial layer; and transferring remaining material after removal of the Nb2N sacrificial layer and the Ta2N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.

Abstract: The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a Nb2N sacrificial layer on an original substrate, and growing a GaN insertion layer on the Nb2N sacrificial layer; growing a Ta2N sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the Ta2N sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the Nb2N sacrificial layer and the Ta2N sacrificial layer; and transferring remaining material after removal of the Nb2N sacrificial layer and the Ta2N sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.

Abstract: A parallel bus phase correction method and a device are provided. The method comprises: correcting a data bus, respectively performing phase correction tests on a clock line; determining a first optimal window of the clock line according to the clock test results; correcting the clock line by using a median value of the first optimal window, respectively performing phase correction tests on the data bus according to the multiple second phase adjustment values, and recording corresponding data test results; determining a second optimal window of the data bus according to the data test results; and performing phase correction on normal data transmission on the basis of the median value of the first optimal window and the median value of the second optimal window. The method achieves phase correction and ensures the correctness and accuracy of data transmission, even if a small clock offset is present.

Abstract: A parallel bus phase correction method and a device are provided. The method comprises: correcting a data bus, respectively performing phase correction tests on a clock line; determining a first optimal window of the clock line according to the clock test results; correcting the clock line by using a median value of the first optimal window, respectively performing phase correction tests on the data bus according to the multiple second phase adjustment values, and recording corresponding data test results; determining a second optimal window of the data bus according to the data test results; and performing phase correction on normal data transmission on the basis of the median value of the first optimal window and the median value of the second optimal window. The method achieves phase correction and ensures the correctness and accuracy of data transmission, even if a small clock offset is present.