Patents by Inventor Hongwei Duan

Hongwei Duan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965420
    Abstract: Disclosed are a shield tunnel segment structure and a construction method thereof. The shield tunnel segment structure includes segment blocks sequentially spliced in a circumferential direction. Each segment block forms a closed annular segment structure, and outer diameters of adjacent annular segment structures gradually increase in an axial direction. At least two adjacent segment blocks of the same annular segment structure form an annular inner groove, and at least one segment block of the adjacent annular segment structures is provided with an inner bump which matches the annular inner groove. At least two adjacent segment blocks of the same annular segment structure form an annular outer groove, and at least one segment block of the adjacent annular segment structures is provided with an outer bump which matches the annular outer groove. The annular outer grooves and the annular inner grooves are staggered in the circumferential direction.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: April 23, 2024
    Assignees: Shandong University, Northeast Electric Power University
    Inventors: Ke Wu, Tao Yang, Yang Zheng, Guodong Li, Zhihao Xing, Hongna Yang, Jiaxiang Xu, Rong Chen, Dongxue Hao, Jizheng Sun, Jingchuan Duan, Hongwei Zhang
  • Patent number: 11949430
    Abstract: An LDPC encoding method and a system for error code detection. In the method and system, partial syndromes using a user portion and a low density parity check matrix are calculated, a parity portion of a codeword is calculated using the partial syndromes and using a quasi-cyclic matrix, the parity portion is generated by segment processing of the quasi-cyclic matrix, and the user portion and the parity portion are concatenated to complete the codeword.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: April 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Haobo Wang, Hongwei Duan
  • Publication number: 20240106460
    Abstract: To improve error correction when errors occur in consecutive bits of user data, the user data can be stored in an interleaved manner. Data of a data unit can be interleaved to generate a permutated data unit. A checksum of the permutated data unit can then be calculated, and an error correction code can be generated over the data unit and the checksum. The error correction code can also be interleaved to generate a permutated error correction code. The permutated data unit, the checksum, and the permutated error correction code can then be concatenated to generate a storage data unit for storage in a memory.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Fan Zhang, Hongwei Duan, Haobo Wang
  • Publication number: 20240080046
    Abstract: An LDPC encoding method and a system for error code detection. In the method and system, partial syndromes using a user portion and a low density parity check matrix are calculated, a parity portion of a codeword is calculated using the partial syndromes and using a quasi-cyclic matrix, the parity portion is generated by segment processing of the quasi-cyclic matrix, and the user portion and the parity portion are concatenated to complete the codeword.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Inventors: Fan ZHANG, Haobo WANG, Hongwei DUAN
  • Publication number: 20240080042
    Abstract: A method for operating an MS decoder and an associated memory system utilizing the MS decoder. The method determines an operation mode of the MS decoder. For each variable node, the method calculates a variable to check node V2C message. The method stores, in a check node unit CNU memory, check information associated with the calculated V2C message according to the operation mode. The check information includes full information when the operation mode is a high precision mode, and partial information when the operation mode is a low precision mode.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Inventors: Fan ZHANG, Hongwei DUAN, Haobo WANG
  • Publication number: 20230191825
    Abstract: An aspect of the disclosure relates to a thin film including an amorphous array of particles including a top surface and a bottom surface opposing each other, the thin film exhibiting thin film interference and further coherent scattering from the amorphous array of particles, wherein the thin film may include first regions and second regions, wherein the thin film interference of the second regions may be suppressed as compared to the first regions. Another aspect of the disclosure relates to a product including an indicium including a thin film in accordance with any of the previous claims, wherein the indicium may include an encoded pattern encoded by the relative position of the second regions to the first regions, wherein the encoded pattern may be visible under specular reflection of light of a pre-determined wavelength. Another aspect of the disclosure relates to a method of producing a thin film.
    Type: Application
    Filed: May 6, 2021
    Publication date: June 22, 2023
    Inventors: Hongwei DUAN, Ling BAI
  • Patent number: 11664821
    Abstract: Techniques related to improving the error floor performance of a bit flipping (BF) decoder are described. In some examples, error floor performance is improved through determining a set of unreliable check nodes (CNs) and using information about the set of unreliable CNs to compute the flipping energies of variable nodes (VNs). In this manner, the flipping energies can be computed more accurately, thereby lowering the error floor. The set of unreliable CNs can be built through applying various criteria, such as criteria relating to the path length to an unsatisfied CN, the degree of a VN in a path to an unsatisfied CN, and/or checksum value. Path length and VN degree can be applied as selection criteria to determine which CNs qualify as members of the set of unreliable CNs. Checksum value can be applied as a trigger condition for building and/or using the set of unreliable CNs.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: May 30, 2023
    Assignee: SK hynix Inc.
    Inventors: Meysam Asadi, Hongwei Duan, Aman Bhatia, Fan Zhang
  • Publication number: 20220332892
    Abstract: There is provided a ?-peptido sugar-copolymer having the structure of formula (I) as defined herein, or a stereoisomer, a tautomer, an N-oxide, a hydrate, a solvate, or a salt thereof, or a mixture of the same. There is provided a process to make the ?-peptido sugar-copolymer as defined herein. There are further provided medical applications of the ?-peptido sugar-copolymer as defined herein. In a preferred embodiment, a block-like copolymer poly(amido-D-glucose)-block-poly-?-(L)-homolysine (PDGu-b-PBLK) synthesized via anionic ring-opening polymerization (ROP) demonstrates an antimicrobial efficacy, an enhanced selectivity towards different bacteria, biocompatibility vs. mammalian cells and spontaneous assembly.
    Type: Application
    Filed: January 12, 2018
    Publication date: October 20, 2022
    Inventors: Bee Eng Mary CHAN, Yu DU, Rubi ZAMUDIO VAZQUEZ, Kaixi ZHANG, Zhangyong SI, Yuguang MU, Hongwei DUAN
  • Publication number: 20220213232
    Abstract: The invention relates to a compound of formula Ia and/or formula Ib: or a pharmaceutically acceptable salt, solvate or prodrug thereof, where the groups are defined herein. The invention also relates to a pharmaceutical formulation comprising the compound for treating or detecting a microbial infection in a subject, a method of determining antimicrobial resistance of a microbial infection using the compound, and a method of determining an effective dose of one or more antimicrobial agents to kill a microorganism using the compound.
    Type: Application
    Filed: September 19, 2019
    Publication date: July 7, 2022
    Inventors: Xuewei LIU, Bee Eng Mary CHAN, Hongwei DUAN, Jingxi HE, Kim LE MAI HOANG, Liang YANG
  • Patent number: 11316532
    Abstract: Devices, systems and methods for improving decoding operations of a decoder are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising N columns, wherein each of at least B columns of the parity matrix has a column weight that exceeds a predetermined column weight, processing the N columns based on a message passing algorithm, and determining, based on the processing, a candidate version of the transmitted codeword, wherein the processing for each of the N columns comprises performing a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation on the first set and the second set, the read operation and the CNU operation on each of the at least B columns spanning two or more time-steps.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Michael Hsu, Hongwei Duan, Aman Bhatia
  • Patent number: 11281276
    Abstract: A control of a memory system includes firmware and one error correction code (ECC) module. The module includes a power control engine and ECC components, each ECC component including a power monitor and a power controller. The firmware configures a window of time and a power consumption rate of a select ECC component depending on characteristics of the memory system. The power monitor of the select ECC component measures a power consumption of the select ECC component within the window. The power control engine receives the measurement of power consumption, decides a next power level for the select ECC component, and controls the power controller of the select ECC component such that the select ECC component operates at the next power level.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: March 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Hongwei Duan, Aman Bhatia
  • Patent number: 11185836
    Abstract: A method for preparing a magnetic chain structure is provided. The method comprises providing a plurality of magnetic particles; dispersing the plurality of magnetic particles in a solution comprising a dopamine-based material to form a reaction mixture; applying a magnetic field across the reaction mixture to align the magnetic particles in the reaction mixture; and polymerizing the dopamine-based material on the aligned magnetic particles to obtain the magnetic chain structure. A magnetic chain structure prepared by the method is also provided.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: November 30, 2021
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Hongwei Duan, Jiajing Zhou, Yee Cheong Lam, Chun Yee Lim, Qirong Xiong
  • Publication number: 20210263577
    Abstract: A control of a memory system includes firmware and one error correction code (ECC) module. The module includes a power control engine and ECC components, each ECC component including a power monitor and a power controller. The firmware configures a window of time and a power consumption rate of a select ECC component depending on characteristics of the memory system. The power monitor of the select ECC component measures a power consumption of the select ECC component within the window. The power control engine receives the measurement of power consumption, decides a next power level for the select ECC component, and controls the power controller of the select ECC component such that the select ECC component operates at the next power level.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Inventors: Fan ZHANG, Hongwei DUAN, Aman BHATIA
  • Patent number: 11043969
    Abstract: Disclosed are devices, systems and methods improving the convergence of a soft bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of an LDPC code and provided to a communication channel prior to reception by the soft bit-flipping decoder, generating, based on the noisy codeword, one or more messages for passing between a plurality of variable nodes and a plurality of check nodes of the soft bit-flipping decoder, generating a reliability metric for each of the one or more messages, storing the reliability metric only for messages comprising magnitudes that are less than or equal to a predetermined threshold value; and performing, based on the one or more messages and the associated reliability metric for at least one of the one more messages, a single decoding iteration of the soft bit-flipping decoder.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: June 22, 2021
    Assignee: SK hynix Inc.
    Inventors: Meysam Asadi, Fan Zhang, Haobo Wang, Hongwei Duan
  • Patent number: 11018695
    Abstract: Disclosed are devices, systems and methods improving the convergence of a bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of a low-density parity-check code and provided to a communication channel prior to reception by the bit-flipping decoder, and performing a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages. In some embodiments, performing a single decoding iteration includes computing a metric corresponding to a single column of the parity check matrix, flipping at least one bit in the single column upon a determination that the metric exceeds a flipping threshold, computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and updating the flipping threshold upon a determination that the syndrome is not zero.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Chenrong Xiong, Haobo Wang, Hongwei Duan, Jiangnan Xia
  • Publication number: 20210143837
    Abstract: Disclosed are devices, systems and methods improving the convergence of a soft bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of an LDPC code and provided to a communication channel prior to reception by the soft bit-flipping decoder, generating, based on the noisy codeword, one or more messages for passing between a plurality of variable nodes and a plurality of check nodes of the soft bit-flipping decoder, generating a reliability metric for each of the one or more messages, storing the reliability metric only for messages comprising magnitudes that are less than or equal to a predetermined threshold value; and performing, based on the one or more messages and the associated reliability metric for at least one of the one more messages, a single decoding iteration of the soft bit-flipping decoder.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Inventors: Meysam Asadi, Fan Zhang, Haobo Wang, Hongwei Duan
  • Publication number: 20210143836
    Abstract: Disclosed are devices, systems and methods improving the convergence of a bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of a low-density parity-check code and provided to a communication channel prior to reception by the bit-flipping decoder, and performing a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages. In some embodiments, performing a single decoding iteration includes computing a metric corresponding to a single column of the parity check matrix, flipping at least one bit in the single column upon a determination that the metric exceeds a flipping threshold, computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and updating the flipping threshold upon a determination that the syndrome is not zero.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Inventors: Fan Zhang, Chenrong Xiong, Haobo Wang, Hongwei Duan, Jiangnan Xia
  • Patent number: 10933654
    Abstract: According to the present disclosure, an isotropic structural colour printing process is provided. The process comprising (a) providing an ink composition comprising ink particles (such as polymeric particles (e.g. polystyrene), metal-organic frameworks (MOFs) (e.g. ZIF-8)) in a liquid reagent; and (b) depositing the ink composition onto a surface of a substrate (e.g. anodic aluminium oxide membrane, photo papers). Due to capillary action and/or absorption of the liquid reagent, the ink particles form an amorphous arrangement of structures that lead to isotropic structural colour. In the preferred embodiment, the ink particles may further be coated with a catechol group (such as polydopamine). An apparatus for detecting a target substance in the gaseous phase, wherein the apparatus comprises a nanostructure capable of exhibiting a change in isotropic structural colour when one or more molecules of the target substance are entrapped as an indication that the target substance is present, is also provided.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: March 2, 2021
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Hongwei Duan, Ling Bai
  • Publication number: 20190366733
    Abstract: According to the present disclosure, an isotropic structural colour printing process is provided. The process comprising (a) providing an ink composition comprising ink particles (such as polymeric particles (e.g. polystyrene), metal-organic frameworks (MOFs) (e.g. ZIF-8)) in a liquid reagent; and (b) depositing the ink composition onto a surface of a substrate (e.g. anodic aluminium oxide membrane, photo papers). Due to capillary action and/or absorption of the liquid reagent, the ink particles form an amorphous arrangement of structures that lead to isotropic structural colour. In the preferred embodiment, the ink particles may further be coated with a catechol group (such as polydopamine). An apparatus for detecting a target substance in the gaseous phase, wherein the apparatus comprises a nanostructure capable of exhibiting a change in isotropic structural colour when one or more molecules of the target substance are entrapped as an indication that the target substance is present, is also provided.
    Type: Application
    Filed: December 21, 2017
    Publication date: December 5, 2019
    Inventors: Hongwei DUAN, Ling BAI
  • Publication number: 20190079014
    Abstract: A core-shell plasmonic nanogapped nanostructured material is provided. The core-shell nanogapped nanostructured material has a core and at least one shell surrounding the core, wherein the at least one shell comprises a first layer comprising a polymer having a catechol group, wherein the first layer defines the nanogap in the core-shell plasmonic nanostructured material, and a second layer comprises a metal disposed on the first layer. A method of preparing the core-shell plasmonic nanogap nanostructured material, and use of the core-shell plasmonic nanogap nanostructured material are also provided. As an embodiment, a polydopamine covalently bonded to a Raman probe or a fluorescent probe is used to prepare the first layer of the shell in said core-shell plasmonic nanogap nanostructured material, thereafter a gold shell is deposited onto the polydopamine to form a second layer of the shell.
    Type: Application
    Filed: March 24, 2017
    Publication date: March 14, 2019
    Inventors: Hongwei Duan, Jiajing Zhou