Abstract: Provided are a PCIe interrupt processing method and apparatus, a device and a non-transitory readable storage medium, relating to the technical field of computers. The PCIe interrupt processing method comprises: a currently generated internal interrupt signal is acquired; a PCIe interrupt type supported by a current FPGA is determined according to an interrupt vector signal output by a PCIe IP core, so as to determine a corresponding target interrupt processing mechanism according to the PCIe interrupt type; and the internal interrupt signal is processed by means of the target interrupt processing mechanism, and a processing result is input to the PCIe IP core, such that the PCIe IP core sends an interrupt message packet to a central processing unit on the basis of the processing result. The technical solution expands the compatibility of an FPGA with processor interrupts, facilitating the implementation of FPGA logic platform construction.

Abstract: The present disclosure relates to data processing, and in particular, to a system for processing a full-stack network card task based on FPGA. The system includes: a network interface controller, configured to receive to-be-processed data, and offload a TCP/IP task from the to-be-processed data by a built-in TCP offload engine, to obtain first processed data; an SSL/TLS protocol processing module, configured to receive the first processed data, and offload an SSL/TLS protocol task from the first processed data, to obtain second processed data; a PR region, configured to receive the second processed data; and a reconfiguration module, configured to acquire, by a host, dynamic configuration information of the PR region, and configure the PR region based on the dynamic configuration information, so that the PR region offloads and processes computation-intensive tasks in the second processed data.

Abstract: A heterogeneous acceleration method, including the following steps: analyzing a received target data packet to obtain data source end identification information; when the data source end identification information does not exist in a configuration information table, customizing a data message format according to the target data packet to obtain a target data message format, or when the data source end identification information exists in the configuration information table, reading the target data message format from the configuration information table; and according to the target data message format, performing acceleration processing on the target data packet to obtain processed data, and returning the processed data to a data source end.

Abstract: A heterogeneous acceleration method, including the following steps: analyzing a received target data packet to obtain data source end identification information; when the data source end identification information does not exist in a configuration information table, customizing a data message format according to the target data packet to obtain a target data message format, or when the data source end identification information exists in the configuration information table, reading the target data message format from the configuration information table; and according to the target data message format, performing acceleration processing on the target data packet to obtain processed data, and returning the processed data to a data source end.

Abstract: Disclosed is a method for accelerated computation of data. The method includes: acquiring, by an accelerating device, computation acceleration control information from a memory of a host, and the computation acceleration control information includes input parameter address information and computation configuration information; acquiring, based on the input parameter address information, parameters to be computed from the memory of the host; and controlling, based on the computation configuration information, a computation unit to perform a computation operation on the parameters to be computed, and obtaining a computation result.

Abstract: The present disclosure relates to data processing, and in particular, to a system for processing a full-stack network card task based on FPGA. The system includes: a network interface controller, configured to receive to-be-processed data, and offload a TCP/IP task from the to-be-processed data by a built-in TCP offload engine, to obtain first processed data; an SSL/TLS protocol processing module, configured to receive the first processed data, and offload an SSL/TLS protocol task from the first processed data, to obtain second processed data; a PR region, configured to receive the second processed data; and a reconfiguration module, configured to acquire, by a host, dynamic configuration information of the PR region, and configure the PR region based on the dynamic configuration information, so that the PR region offloads and processes computation-intensive tasks in the second processed data.

Abstract: Provided are a communication method and system for a distributed heterogeneous acceleration platform, a device and a medium. The method includes: after starting a collaborative acceleration task, determining, by a first target heterogeneous acceleration card in a distributed heterogeneous acceleration platform, a second target heterogeneous acceleration card from the distributed heterogeneous acceleration platform by querying an information table corresponding to the collaborative acceleration task; generating, by the first target heterogeneous acceleration card, a target data packet according to a predefined data packet format, and sending the target data packet to the second target heterogeneous acceleration card via a PCIE interface; and parsing, by the second target heterogeneous acceleration card, the target data packet according to the data packet format, and executing a corresponding read operation or write operation according to a parsing result, so as to complete the collaborative acceleration task.

Abstract: A remote mapping method, apparatus and device for computing resources, and a storage medium, which are applied to a server. Said method comprises: identifying each FPGA heterogeneous accelerator card in an FPGA BOX; establishing a network communication connection with each FPGA heterogeneous accelerator card via a network interface of each FPGA heterogeneous accelerator card in the FPGA BOX, and establishing a network communication connection between FPGA heterogeneous accelerator cards; mapping each FPGA heterogeneous accelerator card to the server; establishing network transmission for the established network communication connections, and migrating a control flow and a data flow that are performed by the PCIE to the network transmission; and deploying a target application in the FPGA BOX through the established network transmission, and when running the target application, performing data exchange with the FPGA BOX via the network transmission.

Abstract: A remote mapping method, apparatus and device for computing resources, and a storage medium, which are applied to a server. Said method comprises: identifying each FPGA heterogeneous accelerator card in an FPGA BOX; establishing a network communication connection with each FPGA heterogeneous accelerator card via a network interface of each FPGA heterogeneous accelerator card in the FPGA BOX, and establishing a network communication connection between FPGA heterogeneous accelerator cards; mapping each FPGA heterogeneous accelerator card to the server; establishing network transmission for the established network communication connections, and migrating a control flow and a data flow that are performed by the PCIE to the network transmission; and deploying a target application in the FPGA BOX through the established network transmission, and when running the target application, performing data exchange with the FPGA BOX via the network transmission.

Abstract: A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Abstract: A method and apparatus for performing a power stress test on an FPGA acceleration card and a computer-readable storage medium. The method includes: dividing, according to a partial reconfiguration method, a hardware resource of an FPGA acceleration card into a static region serving as a hardware logic implementation region for performing a normal function test, and a dynamic PR region including a blank mode occupying no hardware resource and a power test mode for performing a power stress test, and burning FPGA firmware having a partial reconfiguration function to a flash memory; upon receiving a request for power stress test, configuring an operation mode of the dynamic PR region to be the power test mode, loading, to the dynamic PR region, a dynamic PR configuration file burned in the flash memory; and calling a power stress test module to execute the power stress test in the dynamic PR region.

Abstract: Disclosed are a method for data synchronization between a host side and a Field Programmable Gate Array (FPGA) accelerator, a Bidirectional Memory Synchronize Engine (DMSE), a FPGA accelerator, and a data synchronization system. The method includes: in response to detection of data migration from a host side to a preset memory space, generating second state information according to first state information in a first address space, and writing the second state information to a second address space (S201); and in response to detection of the second state information in the second address space, calling Direct Memory Access (DMA) to migrate data in the preset memory space to a memory space of a FPGA accelerator, and copying the second state information to the first address space, so as to implement synchronization (S202).

Abstract: The method includes: an FPGA board feeds back the quantity of controllers and the total quantity of DDR memories after receiving a hardware information acquisition request from a host; after a data space application request is received from the host, on the basis of the data space application request, perform data slice processing on data to be calculated, wherein the data space application request carries the dedicated application space capacity of each DDR and the data to be calculated, and the total quantity of slices of the data to be calculated is the same as the total quantity of DDR memories; and transmit each sliced data to a corresponding DDR space, and according to a data storage position of the sliced data in each DDR, read the data from the DDR memory space in parallel by means of the plurality of controllers and calculate same.

Abstract: A method and apparatus for performing a power stress test on an FPGA acceleration card and a computer-readable storage medium. The method includes: dividing, according to a partial reconfiguration method, a hardware resource of an FPGA acceleration card into a static region serving as a hardware logic implementation region for performing a normal function test, and a dynamic PR region including a blank mode occupying no hardware resources and a power test mode for performing a power stress test, and burning FPGA firmware having a partial reconfiguration function to a flash memory; upon receiving a request for power stress test, configuring an operation mode of the dynamic PR region to be the power consumption test mode, loading, to the dynamic PR region, a dynamic PR configuration file burned in the flash memory; and calling a power stress test module to execute the power stress test in the dynamic PR region.

Abstract: The method includes: an FPGA board feeds back the quantity of controllers and the total quantity of DDR memories after receiving a hardware information acquisition request from a host; after a data space application request is received from the host, on the basis of the data space application request, perform data slice processing on data to be calculated, wherein the data space application request carries the dedicated application space capacity of each DDR and the data to be calculated, and the total quantity of slices of the data to be calculated is the same as the total quantity of DDR memories; and transmit each sliced data to a corresponding DDR space, and according to a data storage position of the sliced data in each DDR, read the data from the DDR memory space in parallel by means of the plurality of controllers and calculate same.

Abstract: Disclosed are a method for data synchronization between a host side and a Field Programmable Gate Array (FPGA) accelerator, a Bidirectional Memory Synchronize Engine (DMSE), a FPGA accelerator, and a data synchronization system. The method includes: in response to detection of data migration from a host side to a preset memory space, generating second state information according to first state information in a first address space, and writing the second state information to a second address space (S201); and in response to detection of the second state information in the second address space, calling Direct Memory Access (DMA) to migrate data in the preset memory space to a memory space of a FPGA accelerator, and copying the second state information to the first address space, so as to implement synchronization (S202).

Abstract: A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Abstract: A data processing method, a data processing apparatus, a distributed data flow programming framework, an electronic device, and a storage medium. The data processing method includes: dividing a data processing task into a plurality of data processing subtasks (S101); determining, in a Field Programmable Gate Array (FPGA) accelerator side, a target FPGA acceleration board corresponding to each of the data processing subtasks (S102); and sending data to be computed to the target FPGA acceleration board, and executing the corresponding data processing subtask by use of each of the target FPGA acceleration boards to obtain a data processing result (S103). According to the method, a physical limitation of host interfaces on the number of FPGA acceleration boards in an FPGA accelerator side may be avoided, thereby improving the data processing efficiency.

Abstract: The present invention is about a data transmission method and a ping-pong DMA architecture. The method includes: acquiring the current state of an initialized register, determining a state type corresponding to the current state of the register, and performing an operation corresponding to the state type based on the state type determined by the register, the state type includes an initialization state, a state that the first DMA module is used, and a state that the second DMA module is used, the state that the first DMA module is used means a state when a previous batch of data is transmitted by the first DMA module, and the state that the second DMA module is used means a state when the previous batch of data is transmitted by the second DMA module.

Abstract: A method, an apparatus, a device and a medium for processing data based on an FPGA are provided. In the method, computing circuit resources of the FPGA are divided into N DPR spaces based on a preset space threshold, where N is a positive integer greater than 1. When a target type of data is acquired, a corresponding number of the DPR spaces are selected and target firmware corresponding to the target type is loaded into the selected DPR spaces. Then the target firmware is executed to process the target type of data.