Patents by Inventor Hongxi Liu

Hongxi Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11927659
    Abstract: Disclosed is a method and apparatus for frequency drift correction of magnetic resonance CEST imaging, and a medium and an imaging device. The method comprises the following steps: firstly, in the frequency drift correction module, exciting a target slice by using a small flip-angle radio-frequency pulse, and acquiring a single line of free induction decay signals or two lines of non-phase encoding gradient echo signals; secondly, respectively calculating a value of the main magnetic field frequency drift according to phase information and an acquisition time of the single line of free induction decay signals or the two lines of non-phase encoding gradient echo signals; then adjusting the center frequency of the magnetic resonance device in real time according to the calculated value of the main magnetic field frequency drift, and achieving the real-time correction of main magnetic field frequency drift; and finally, performing CEST imaging.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: March 12, 2024
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Yi Zhang, Ruibin Liu, Hongxi Zhang, Dan Wu
  • Patent number: 11850659
    Abstract: The present disclosure discloses a high-entropy alloy powder for laser cladding and a use method thereof. The alloy powder is CoCrFeMnNiCx, and x has a value of 0.1-0.15. The specific method includes: subjecting a 45 steel substrate to surface pretreatment, mixing the weighed CoCrFeMnNi high-entropy alloy powder with different content of a nano-C powder uniformly and pre-placed on the pre-treated substrate surface to form a prefabricated layer, then placing the prefabricated layer at 80-90° C. for constant temperature treatment for 8-12 h, and under a protective atmosphere, subjecting the cladding powder to laser cladding on the surface of the 45 steel. The method of the present disclosure prepares a CoCrFeMnNiCx high-entropy alloy coating with performance superior to the CoCrFeMnNi high-entropy alloy coating.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: December 26, 2023
    Assignee: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Hongxi Liu, Jingzhou Liu, Xuanhong Hao, Yingnan Di, Jianquan Lin
  • Publication number: 20220097133
    Abstract: The present disclosure discloses a high-entropy alloy powder for laser cladding and a use method thereof. The alloy powder is CoCrFeMnNiCx, and x has a value of 0.1-0.15. The specific method includes: subjecting a 45 steel substrate to surface pretreatment, mixing the weighed CoCrFeMnNi high-entropy alloy powder with different content of a nano-C powder uniformly and pre-placed on the pre-treated substrate surface to form a prefabricated layer, then placing the prefabricated layer at 80-90° C. for constant temperature treatment for 8-12 h, and under a protective atmosphere, subjecting the cladding powder to laser cladding on the surface of the 45 steel. The method of the present disclosure prepares a CoCrFeMnNiCx high-entropy alloy coating with performance superior to the CoCrFeMnNi high-entropy alloy coating.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 31, 2022
    Applicant: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Hongxi LIU, Jingzhou LIU, Xuanhong HAO, Yingnan DI, Jianquan LIN
  • Publication number: 20200194498
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
  • Patent number: 10629650
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
  • Publication number: 20200075668
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.
    Type: Application
    Filed: August 29, 2018
    Publication date: March 5, 2020
    Inventors: Hongxi Liu, Baolei Wu, Narayanapillai Kulothungasagaran, Subash Pattabiraman Lakshmipathi, Yew Tuck Clament Chow, Curtis Chun-I Hsieh, Yi Jiang, Jin Ho Lee, Yong Wee Francis Poh
  • Publication number: 20180182809
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, the integrated circuit includes a plurality of magnetic random access memory (MRAM) structures. Each of the MRAM structures includes a bottom electrode. The MRAM structures further include a magnetic tunnel junction stack (MTJ stack) overlying and in electrical communication with the bottom electrode. The MRAM structures also include a top electrode layer overlying and in electrical communication with the MTJ stack. The integrated circuit further includes a spin-on dielectric layer at least partially encapsulating the MRAM structures with the spin-on dielectric layer disposed between adjacent MRAM structures.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventors: Hongxi Liu, Chenchen Jacob Wang, Yew Tuck Clament Chow, Narayanapillai Kulothungasagaran, Yong Wee Francis Poh, Jin Ho Lee, Jianbo Yang