Abstract: A device for detecting soil nutrients on site, including an extracting grid, an on-site real-time detection assembly and a transfer assembly for transferring a soil extract from the extracting grid to the on-site real-time detection assembly. A soil nutrient detection method using the device and a microfluidic chip are also provided. The microfluidic chip includes a cover plate and a base plate. The base plate includes a soil extract feeding groove, a quantitative feeding groove, a reagent storage groove, and a serpentine groove.

Abstract: Disclosed are an array substrate, a display panel and a display. The array substrate is provided with a thin film transistor and a gate driving circuit. A trigger signal input terminal of the gate driving circuit corresponds to an output terminal of the thin film transistor, a first insulating layer is provided between a first metal layer corresponding to the output terminal of the thin film transistor and a second metal layer corresponding to the trigger signal input terminal of the gate driving circuit. A projected area of the first metal layer on the first insulating layer is partially overlapped with a projected area of the second metal layer on the first insulating layer.

Abstract: A base substrate and a first metal layer laminated on the base substrate are included. A first laminated portion and a second laminated portion are arranged on and directly contact a side of the first metal layer. The first laminated portion includes a first insulating layer, a second metal layer, a second insulating layer and a first conductive layer. The first laminated portion is arranged with a first via. The second laminated portion includes a third insulating layer and a second conductive layer laminated on the third insulating layer. The second laminated portion is arranged with a second via. The first via is connected to the first conductive layer, the second via is connected to the second conductive layer, and the first conductive layer is connected to the second conductive layer. The second laminated portion is extended to reach an edge of the first metal layer.

Abstract: A backlight module and display device, related to the display field. The backlight module includes a plurality of light-emitting elements and a controller, where the plurality of light-emitting elements serve as light sources for a plurality of sub-pixels respectively; and the controller is configured to control a brightness of each of the plurality of light-emitting elements. When the backlight module is in operation, if an i-th data line does not need to charge one of a plurality of sub-pixels connected to the i-th data line, the controller increases the brightness of the light-emitting element corresponding to a next sub-pixel when the next sub-pixel emits light. In this way, each sub-pixel can have an actual gray scale that reaches a target gray scale thereof, so that the uniformity of brightness of the display panel is improved.

Abstract: A backlight module and display device, related to the display field. The backlight module includes a plurality of light-emitting elements and a controller, where the plurality of light-emitting elements serve as light sources for a plurality of sub-pixels respectively; and the controller is configured to control a brightness of each of the plurality of light-emitting elements. When the backlight module is in operation, if an i-th data line does not need to charge one of a plurality of sub-pixels connected to the i-th data line, the controller increases the brightness of the light-emitting element corresponding to a next sub-pixel when the next sub-pixel emits light. In this way, each sub-pixel can have an actual gray scale that reaches a target gray scale thereof, so that the uniformity of brightness of the display panel is improved.

Abstract: Disclosed are an array substrate, a display panel and a display. The array substrate is provided with a thin film transistor and a gate driving circuit. A trigger signal input terminal of the gate driving circuit corresponds to an output terminal of the thin film transistor, a first insulating layer is provided between a first metal layer corresponding to the output terminal of the thin film transistor and a second metal layer corresponding to the trigger signal input terminal of the gate driving circuit. A projected area of the first metal layer on the first insulating layer is partially overlapped with a projected area of the second metal layer on the first insulating layer.

Abstract: Provided are an antibody or antigen-binding fragment thereof that specifically binds to hepatitis B virus surface antigen (HBsAg), a pharmaceutical composition containing the antibody or antigen-binding fragment, and use thereof. Further provided are a nucleic acid molecule encoding the antibody, a vector and a host cell containing the nucleic acid molecule, and a method for preparing the antibody.

Abstract: A base substrate and a first metal layer laminated on the base substrate are included. A first laminated portion and a second laminated portion are arranged on and directly contact a side of the first metal layer. The first laminated portion includes a first insulating layer, a second metal layer, a second insulating layer and a first conductive layer. The first laminated portion is arranged with a first via. The second laminated portion includes a third insulating layer and a second conductive layer laminated on the third insulating layer. The second laminated portion is arranged with a second via. The first via is connected to the first conductive layer, the second via is connected to the second conductive layer, and the first conductive layer is connected to the second conductive layer. The second laminated portion is extended to reach an edge of the first metal layer.

Abstract: The present disclosure discloses a pixel structure, an array substrate and a display panel. The pixel structure includes a first data line; a first gate line and a second gate line; a first pixel unit and a second pixel unit. The first pixel units and second pixel units arranged along a second direction; a first pixel electrode relative to the second pixel electrode is close to the first data line, a first thin film transistor and second thin film transistors are arranged close to the first data line; first connecting trace is set between the first drain electrode and the first pixel electrode, a second connecting trace is set between the second drain electrode and the second pixel electrode to make a capacitance of the first pixel unit matching with a capacitance of the second pixel unit.

Abstract: The present disclosure provides a pixel electrode and a display panel. The pixel electrode includes a trunk portion including a first trunk and a second trunk and branch portions. The first trunk and the second trunk are pixel electrode areas. An intersection point of the first trunk and the second trunk is a central point of the trunk portion. the first trunk intersects with the second trunk to form four equal pixel electrode areas and the four pixel areas are four branch portions. Each of the four branch portions includes a plurality of branches. An end of each branch or an end of an extension line thereof intersects with the first trunk or an extension line thereof. An other end of each branch or an other end of the extension line thereof intersects with the second trunk or an extension line thereof.

Abstract: The present disclosure provides a display panel, a driving method for a display panel, and a display device. The driving method for the display panel includes a first column of pixels and a second column of pixels. When charging the second column of pixels corresponding to a 2nth row of scanning lines, the second column of pixels corresponding to a (2n+4)th row of scanning lines is pre-charged.

Abstract: The present disclosure discloses a pixel structure, an array substrate and a display panel. The pixel structure includes a first data line; a first gate line and a second gate line; a first pixel unit and a second pixel unit. The first pixel units and second pixel units arranged along a second direction; a first pixel electrode relative to the second pixel electrode is close to the first data line, a first thin film transistor and second thin film transistors are arranged close to the first data line; first connecting trace is set between the first drain electrode and the first pixel electrode, a second connecting trace is set between the second drain electrode and the second pixel electrode to make a capacitance of the first pixel unit matching with a capacitance of the second pixel unit.

Abstract: The present disclosure provides a pixel electrode and a display panel. The pixel electrode includes a trunk portion including a first trunk and a second trunk and branch portions. The first trunk and the second trunk are pixel electrode areas. An intersection point of the first trunk and the second trunk is a central point of the trunk portion. the first trunk intersects with the second trunk to form four equal pixel electrode areas and the four pixel areas are four branch portions. Each of the four branch portions includes a plurality of branches. An end of each branch or an end of an extension line thereof intersects with the first trunk or an extension line thereof. An other end of each branch or an other end of the extension line thereof intersects with the second trunk or an extension line thereof.

Abstract: The present disclosure provides a display panel, a driving method for a display panel, and a display device. The driving method for the display panel includes a first column of pixels and a second column of pixels. When charging the second column of pixels corresponding to a 2nth row of scanning lines, the second column of pixels corresponding to a (2n+4)th row of scanning lines is pre-charged.

Abstract: The present disclosure provides an array substrate, a display panel, and a display device. The display panel includes an array substrate, the array substrate includes: a display unit; a drive unit; a fan out area, located between the display unit and the drive unit, the fan out area defines a fan out wire group, the fan out wire group is configured to connect the display unit and the drive unit; and a virtual line, defined at at least one side of the fan out wire group and adjacent to a fan out wire at the outermost of the fan out wire group.