Patents by Inventor Hong-Yi Wu
Hong-Yi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240076797Abstract: A susceptor assembly for supporting a crucible during a crystal growth process includes a susceptor base, a tubular sidewall connected to the susceptor base, and a removable sacrifice ring interposed between the susceptor base and the sidewall. Each of the susceptor base and the sidewall is formed of a carbon-containing material. The susceptor base has an annular wall and a shoulder extending radially outward from an outer surface of the annular wall. The sidewall has a first end that receives the annular wall to connect the sidewall to the susceptor base. The sacrifice ring has a first surface that faces the outer surface of the annular wall, a second surface that faces an interior surface of the sidewall, and a ledge extending outward from the second surface that engages the first end of the sidewall.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventors: Hong-Huei Huang, Benjamin Michael Meyer, Chun-Sheng Wu, Wei-Chen Chou, Chen-Yi Lin, Feng-Chien Tsai
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Patent number: 11360709Abstract: A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.Type: GrantFiled: November 20, 2020Date of Patent: June 14, 2022Assignee: FARADAY TECHNOLOGY CORPORATIONInventors: Hong-Yi Wu, Sivaramakrishnan Subramanian, Sridhar Cheruku, Ko-Ching Chao
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Publication number: 20220164136Abstract: A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.Type: ApplicationFiled: November 20, 2020Publication date: May 26, 2022Inventors: Hong-Yi WU, Sivaramakrishnan SUBRAMANIAN, Sridhar CHERUKU, Ko-Ching CHAO
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Patent number: 11145343Abstract: A method for controlling a multi-cycle write leveling process in a memory system is provided. After a write leveling process is completed and before a write training process is performed, the multi-cycle write leveling process is performed. Consequently, when a DDR memory of the memory system receives a clock signal and a first data strobe signal, the DDR memory can confirm that the signal edges of the clock signal and the first data strobe signal are aligned with each other and the signal edges are accurate.Type: GrantFiled: November 20, 2020Date of Patent: October 12, 2021Assignee: FARADAY TECHNOLOGY CORPORATIONInventors: Sivaramakrishnan Subramanian, Hong-Yi Wu, Sridhar Cheruku, Ko-Ching Chao
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Patent number: 9716090Abstract: A FinFET structure includes a substrate, a plurality of stripes, a metal gate and an oxide material. The stripes are on the substrate. The metal gate is on a sidewall and a top surface of one of the stripes. The oxide material is between the metal gate and the stripes. An average roughness of an interface between the metal gate and the oxide material is in a range of from about 0.1 nm to about 0.2 nm.Type: GrantFiled: June 27, 2016Date of Patent: July 25, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheng-Ta Wu, Cheng-Wei Chen, Hong-Yi Wu, Shiu-Ko Jangjian, Wei-Ming You, Ting-Chun Wang
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Publication number: 20160307895Abstract: A FinFET structure includes a substrate, a plurality of stripes, a metal gate and an oxide material. The stripes are on the substrate. The metal gate is on a sidewall and a top surface of one of the stripes. The oxide material is between the metal gate and the stripes. An average roughness of an interface between the metal gate and the oxide material is in a range of from about 0.1 nm to about 0.2 nm.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: CHENG-TA WU, CHENG-WEI CHEN, HONG-YI WU, SHIU-KO JANGJIAN, WEI-MING YOU, TING-CHUN WANG
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Patent number: 9406675Abstract: A semiconductor structure and a method for forming the same are provided. The method includes providing a substrate, forming a fin structure extruding from the substrate, forming shallow trench isolations over the substrate, and forming an oxide material over the fin structure. The method further includes forming a carbon-doped amorphous silicon layer or a carbon-doped poly silicon layer over the oxide material, wherein the forming a carbon-doped amorphous silicon layer or a carbon-doped poly silicon layer includes doping carbon in a range of from about 5E19/cm3 to about 1E22/cm3.Type: GrantFiled: March 16, 2015Date of Patent: August 2, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheng-Ta Wu, Cheng-Wei Chen, Hong-Yi Wu, Shiu-Ko Jangjian, Wei-Ming You, Ting-Chun Wang
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Publication number: 20120289069Abstract: An input/output (I/O) interface blocking device includes a fitting member. The fitting member includes a protruding portion, which includes a first sidewall and a second sidewall opposite to each other. The first sidewall is slanted in a direction allowing the first fitting member to be inserted into a space in an I/O interface receptacle. The second sidewall is configured to block the fitting member from being pulled out of the space in the I/O interface receptacle.Type: ApplicationFiled: May 13, 2011Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Liang Chueh, Hong-Yi Wu, Yeh-Chieh Wang, Chih-Yee Chen, Jiun-Rong Pai
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Patent number: 7323212Abstract: A dummy dispense of liquid is controlled by recording a time at which a substrate is processed; recording a time at which a liquid is dispensed; comparing the time at which the substrate is processed and the time at which the liquid is dispensed to generate a dummy dispense signal when a dummy dispense is required. A system for controlling dummy dispense of liquid includes at least one information storage device storing a time at which a substrate is processed and a time at which a liquid is dispensed. At least one processor compares the time at which the substrate is processed and the time at which the liquid is dispensed to determine whether a dummy dispense is required.Type: GrantFiled: October 29, 2003Date of Patent: January 29, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hong-Yi Wu, Chih-Jung Weng, Chung-Cheng Ni, Yi-Hsin Yu
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Patent number: 7282122Abstract: A method and system for determining a lifetime of a target for a physical vapor deposition tool (302), has, a mapping table (304a) of criteria for a minimum accumulating rate of ? wafers fabricated by ? target life for a target in the tool; and a database (304) recording ? wafers fabricated by ? target life for a target in the tool; and a computer (306) retrieving the criteria from the mapping table and entering the criteria in the database; and the tool (302) reporting ? wafers fabricated by ? target life for a target in the tool (302) for comparison with the criteria.Type: GrantFiled: March 26, 2004Date of Patent: October 16, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hui Wen Chang, Chang Hui Chao, Hong Yi Wu
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Patent number: 7145459Abstract: A system for manufacturing control using radio frequency identification (RFID). A trigger issues a trigger signal when activated by user contact. A RFID interrogator retrieves information from a RFID tag when activated. A controller is configured to activate the RFID interrogator, get the relative information from associated systems and control the indicator according to the trigger signal. An indicator provides operating status of the RFID interrogator and/or information getting from the controller.Type: GrantFiled: January 7, 2005Date of Patent: December 5, 2006Assignee: Taiwan Semiconductor Manufacturing Co,M Ltd.Inventors: Hong-Yi Wu, James You, Hong-Wen Liao
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Publication number: 20060167571Abstract: A system for manufacturing control using radio frequency identification (RFID). A trigger issues a trigger signal when activated by user contact. A RFID interrogator retrieves information from a RFID tag when activated. A controller is configured to activate the RFID interrogator, get the relative information from associated systems and control the indicator according to the trigger signal. An indicator provides operating status of the RFID interrogator and/or information getting from the controller.Type: ApplicationFiled: January 7, 2005Publication date: July 27, 2006Inventors: Hong-Yi Wu, James You, Hong-Wen Liao
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Publication number: 20050095537Abstract: A dummy dispense of liquid is controlled by recording a time at which a substrate is processed; recording a time at which a liquid is dispensed; comparing the time at which the substrate is processed and the time at which the liquid is dispensed to generate a dummy dispense signal when a dummy dispense is required. A system for controlling dummy dispense of liquid includes at least one information storage device storing a time at which a substrate is processed and a time at which a liquid is dispensed. At least one processor compares the time at which the substrate is processed and the time at which the liquid is dispensed to determine whether a dummy dispense is required.Type: ApplicationFiled: October 29, 2003Publication date: May 5, 2005Inventors: Hong-Yi Wu, Chih-Jung Weng, Chung-Cheng Ni, Yi-Hsin Yu