Abstract: A system for defending against a side channel attack. The system includes a reuse distance buffer configured to measure one or more reuse distances for a microarchitecture block according to information of marker candidates and information of target events of a microarchitecture block; and a defense actuator configured to determine existence of a side channel attack in the microarchitecture block according to the one or more reuse distances for the microarchitecture block.

Abstract: A system and method for defense against cache timing channel attacks using cache management hardware is provided. Sensitive information leakage is a growing security concern exacerbated by shared hardware structures in computer processors. Recent studies have shown how adversaries can exploit cache timing channel attacks to exfiltrate secret information. To effectively guard computing systems against such attacks, embodiments disclosed herein provide practical defense techniques that are readily deployable and introduce only minimal performance overhead. In this regard, a new protection framework against cache timing channel attacks is provided herein by leveraging commercial off-the-shelf (COTS) hardware support in processor caches, including last level caches (LLC), for cache monitoring and partitioning. This framework applies signal processing techniques on per-domain cache occupancy data to identify suspicious application contexts.

Abstract: A system for defending against a side channel attack. The system includes a reuse distance buffer configured to measure one or more reuse distances for a microarchitecture block according to information of marker candidates and information of target events of a microarchitecture block; and a defense actuator configured to determine existence of a side channel attack in the microarchitecture block according to the one or more reuse distances for the microarchitecture block.

Abstract: A system and method for defense against cache timing channel attacks using cache management hardware is provided. Sensitive information leakage is a growing security concern exacerbated by shared hardware structures in computer processors. Recent studies have shown how adversaries can exploit cache timing channel attacks to exfiltrate secret information. To effectively guard computing systems against such attacks, embodiments disclosed herein provide practical defense techniques that are readily deployable and introduce only minimal performance overhead. In this regard, a new protection framework against cache timing channel attacks is provided herein by leveraging commercial off-the-shelf (COTS) hardware support in processor caches, including last level caches (LLC), for cache monitoring and partitioning. This framework applies signal processing techniques on per-domain cache occupancy data to identify suspicious application contexts.