Patents by Inventor Hongzhong Xu
Hongzhong Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118835Abstract: An SSD includes an MRAM, an NAND memory, and an SSD controller. The SSD controller is configured to receive first data from a host machine, save the first data to an SSD data buffer, fetch the first data from the SSD data buffer and write the first data to the MRAM via the MRAM controller, determine, by the data allocation circuit based on a characteristic of the first data, whether to save the first data to the MRAM or the NAND memory, and in response to determining saving the first data to the NAND memory, read the first data from the MRAM, write the first data to the NAND memory, and erase the first data from the MRAM.Type: ApplicationFiled: April 30, 2023Publication date: April 11, 2024Inventors: Fei XUE, Wentao WU, Jiajing JIN, Xiang GAO, Jifeng WANG, Yuming XU, Jiu HENG, Hongzhong ZHENG
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Patent number: 9466712Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.Type: GrantFiled: April 28, 2015Date of Patent: October 11, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Won Gi Min, Hongzhong Xu, Zhihong Zhang, Jiang-Kai Zuo
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Publication number: 20150243781Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.Type: ApplicationFiled: April 28, 2015Publication date: August 27, 2015Inventors: WON GI MIN, HONGZHONG XU, ZHIHONG ZHANG, JIANG-KAI ZUO
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Patent number: 9041103Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.Type: GrantFiled: February 28, 2013Date of Patent: May 26, 2015Assignee: FREESCALE SEMICONDUCTOR, INCInventors: Won Gi Min, Zhihong Zhang, Hongzhong Xu, Jiang-Kai Zuo
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Patent number: 8487398Abstract: A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.Type: GrantFiled: July 14, 2010Date of Patent: July 16, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Hongzhong Xu, Zhihong Zhang, Jiang-Kai Zuo
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Publication number: 20130175616Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.Type: ApplicationFiled: February 28, 2013Publication date: July 11, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: WON GI MIN, ZHIHONG ZHANG, HONGZHONG XU, JIANG-KAI ZUO
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Patent number: 8389366Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80?, 80?), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44?, 84, 84?) and drift (50, 50?, 90, 90?) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50?, 90, 90?) at least into the underlying body region (44, 44? 84, 84?), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50?, 90, 90?).Type: GrantFiled: May 30, 2008Date of Patent: March 5, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Won Gi Min, Hongzhong Xu, Zhihong Zhang, Jiang-Kai Zuo
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Publication number: 20120012970Abstract: A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.Type: ApplicationFiled: July 14, 2010Publication date: January 19, 2012Inventors: HONGZHONG XU, ZHIHONG ZHANG, JIANG-KAI ZUO
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Patent number: 7911750Abstract: An electrostatic discharge (ESD) protection device (41, 51, 61, 71, 81) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (41, 41?, 41?; 71, 71?, 71?), each stage (41, 41?, 41?; 71, 71?, 71?) comprising first (T1, T1?, T1?, etc.) and second transistors (T2, T2?, T2?? etc.) having a common collector (52, 52?, 52?) and first (26, 26?, 26?) and second (36, 36?, 36?) emitters providing terminals (32, 42; 32?, 42?; 32?, 42?) of each clamp stage (41, 41?, 41?; 71, 71?, 71. A first emitter (25) of the first stage (41, 71) couples to the common terminal (23) and a second emitter (42?) of the last stage (41?, 71?) couples to the I/O terminals (22). Zener diode triggers are not used. Integrated external ESD trigger resistors (29, 29?, 29?; 39, 39?, 39?) (e.g.Type: GrantFiled: February 27, 2008Date of Patent: March 22, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Rouying Zhan, Chai Ean E. Gill, James D. Whitfield, Hongzhong Xu
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Patent number: 7701012Abstract: An electrostatic discharge (ESD) protection clamp (61) for I/O terminals (22, 23) of integrated circuits (ICs) (24) comprises an NPN bipolar transistor (25) coupled to an integrated Zener diode (30). Variations in the break-down current-voltage characteristics (311, 312, 313, 314) of multiple prior art ESD clamps (31) in different parts of the same IC chip is avoided by forming the anode (301) of the Zener (30) in the shape of a base-coupled P+ annular ring (75) surrounded by a spaced-apart N+ annular collector ring (70) for the cathode (302) of the Zener (30).Type: GrantFiled: February 26, 2007Date of Patent: April 20, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Hongzhong Xu, Chai Ean Gill, James D. Whitfield, Jinman Yang
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Publication number: 20090294849Abstract: Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80?, 80?), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44?, 84, 84?) and drift (50, 50?, 90, 90?) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50?, 90, 90?) at least into the underlying body region (44, 44? 84, 84?), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50?, 90, 90?).Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Won Gi Min, Zhihong Zhang, Hongzhong Xu, Jiang-Kai Zuo
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Publication number: 20090213506Abstract: An electrostatic discharge (ESD) protection device (41, 51, 61, 71, 81) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (41, 41?, 41?; 71, 71?, 71?), each stage (41, 41+, 41?; 71, 71?, 71?) comprising first (T1, T1?, T1?, etc.) and second transistors (T2, T2?, T2?? etc.) having a common collector (52, 52?, 52?) and first (26, 26?, 26?) and second (36, 36?, 36?) emitters providing terminals (32, 42; 32?, 42?; 32?, 42?) of each clamp stage (41, 41?, 41?; 71, 71?, 71. A first emitter (25) of the first stage (41, 71) couples to the common terminal (23) and a second emitter (42?) of the last stage (41?, 71?) couples to the I/O terminals (22). Zener diode triggers are not used. Integrated external ESD trigger resistors (29, 29?, 29?; 39, 39?, 39?) (e.g.Type: ApplicationFiled: February 27, 2008Publication date: August 27, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Rouying Zhan, Chai Ean Gill, James D. Whitfield, Hongzhong Xu
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Publication number: 20080203534Abstract: An electrostatic discharge (ESD) protection clamp (61) for I/O terminals (22, 23) of integrated circuits (ICs) (24) comprises an NPN bipolar transistor (25) coupled to an integrated Zener diode (30). Variations in the break-down current-voltage characteristics (311, 312, 313, 314) of multiple prior art ESD clamps (31) in different parts of the same IC chip is avoided by forming the anode (301) of the Zener (30) in the shape of a base-coupled P+ annular ring (75) surrounded by a spaced-apart N+ annular collector ring (70) for the cathode (302) of the Zener (30).Type: ApplicationFiled: February 26, 2007Publication date: August 28, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Hongzhong Xu, Chai Ean Gill, James D. Whitfield, Jinman Yang
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Patent number: 7368786Abstract: Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.Type: GrantFiled: March 11, 2005Date of Patent: May 6, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Hongzhong Xu, Richard T. Ida, Vijay Parthasarathy
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Patent number: 7288820Abstract: Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.Type: GrantFiled: December 1, 2004Date of Patent: October 30, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Michael Baird, Richard T. Ida, James D. Whitfield, Hongzhong Xu, Sopan Joshi
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Patent number: 7164566Abstract: Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.Type: GrantFiled: March 19, 2004Date of Patent: January 16, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Hongzhong Xu, Beth A. Baumert, Richard T. Ida
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Publication number: 20060202265Abstract: Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.Type: ApplicationFiled: March 11, 2005Publication date: September 14, 2006Inventors: Hongzhong Xu, Richard Ida, Vijay Parthasarathy
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Publication number: 20050207077Abstract: Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.Type: ApplicationFiled: March 19, 2004Publication date: September 22, 2005Inventors: Hongzhong Xu, Beth Baumert, Richard Ida
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Patent number: 6936896Abstract: A low voltage thyristor is disclosed that can be used to provide protection during electrostatic discharge event. The thyristor is connected between voltage reference nodes having a common potential, such as ground nodes, that are isolated from one another during normal operating conditions. During an ESD event on one of the voltage reference nodes, the low voltage thyrister triggers, at a voltage of less than ten volts, to help discharge the ESD current through the otherwise isolated ground node.Type: GrantFiled: December 21, 2001Date of Patent: August 30, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Richard T. Ida, Hongzhong Xu
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Publication number: 20050093073Abstract: Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.Type: ApplicationFiled: December 1, 2004Publication date: May 5, 2005Inventors: Michael Baird, Richard Ida, James Whitfield, Hongzhong Xu, Sopan Joshi