Abstract: A label printing and attaching system includes a label printing device and a label attaching device. The label printing device has an ink tape supply mechanism for supplying an ink tape with a label pattern. A label tape supply mechanism of the label printing device is adapted to supply a label tape that includes a carrier tape and blank label paper adhered to the carrier tape. The label printing device further includes a heat transfer machine adapted to heat transfer the label pattern on the ink tape onto the blank label paper of the label tape to obtain a desired label. The label attaching device has a label picker adapted to pick up the label with the printed label pattern from the label tape, and a moving device adapted to move the label picker to place the picked label with the printed label pattern onto a product.

Abstract: The invention provides a reaction system for preparing butyraldehyde by propylene carbonylation, comprising: a reactor; a side wall of the reactor is sequentially provided with a catalyst inlet, a propylene inlet and a synthesis gas inlet from top to bottom; the bottom of the reactor is provided with a solvent inlet; two micro-interface generators are arranged inside of the reactor from top to bottom, and the micro-interface generator located at a top end is connected to the propylene inlet to break the propylene gas into micron-scale micro-bubbles; the micro-interface generator located at a bottom is connected to the synthesis gas inlet for breaking the synthesis gas into micron-scale micro-bubbles; the outlets of the two micro-interface generators are opposite, and the outlets are connected with a gas distributor for evenly distributing raw materials.

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic design library including a plurality of design rules. Embodiments may include generating a routing graph, based upon, at least in part, the plurality of design rules, wherein the routing graph is a virtual representation of all of the available routing space for all routing layers associated with an electronic design. Embodiments may further include dynamically updating the routing graph at a graphical user interface, based upon, at least in part, a creation of a routing segment or a via at the graphical user interface.

Abstract: A system, method, and computer program product for predicting mismatch contribution in an electronic environment. Embodiments may include modeling, using a processor, a discrete output mismatch contribution problem using sparse logistic regression to generate a mismatch contribution model and applying a cross-validation approach to increase a complexity of the mismatch contribution model. Embodiments may further include computing one or more mismatch contribution values from the mismatch contribution model and defining at least one sizing constraint or determining a worst case result associated with a sampling process based upon, at least in part, the one or more mismatch contribution values.

Abstract: Disclosed is an improved approach to implement analog or mixed-signal designs. A method, system, and computer program product are provided to fully automate the analog placement step using a virtual grouping methodology which considers variable components and uses a genetic placement algorithm to find the best placement solution which fully respects the analog constraints defined by a user or auto identified by a tool.

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

Abstract: A method for determining the tail performance of an integrated circuit is described. The method includes simulating the integrated circuit over samples to obtain values for circuit specifications and sorting the circuit specifications based on an expected number of samples. The method also includes arranging a sequence of samples from the universe according to a sequence in the group of circuit specifications, simulating the integrated circuit with one of the sequence of samples to obtain at least one circuit specification, removing the at least one circuit specification from the group when it satisfies the stop criterion, and modifying a model for a second circuit specification based on the at least one circuit specification. The computer-implemented method also includes reordering the group of circuit specifications based on the model and determining an integrated circuit performance based on a simulation result for the at least one circuit specification.

Abstract: A method for visualizing a performance distribution of an integrated circuit (IC) design is provided. The method includes determining a yield limit based on a group of Monte Carlo simulations of the IC design, and a functional yield, and selecting an initial yield based on an initial specification value from the group of Monte Carlo simulations. The method also includes selecting additional yield values based on additional specification values and on the group of Monte Carlo simulations of the IC design, wherein the low yield values are estimated using Kernel Density Estimation, and the high yield values are estimated using repeated binary search. The cumulative distribution function and probability density function for a performance of the IC design are estimated based on the additional yield values and the additional specification values. Also, the method includes obtaining a quantile representation for the performance of the IC design from the cumulative distribution function.

Abstract: A system, methods, and a computer program product for estimating a yield and creating corners of a circuit design with the aid of a failure boundary classification. The system, methods and computer program product provide for determining, based on how many sampling factors have failures, whether data samples are sufficient as input to scaled-sigma sampling. If the data samples are insufficient, the failure boundary classification is usable to determine whether the yield is high enough to meet a yield target. A design corner can be located by applying a binary search to results of scaled-sigma sampling. The failure boundary classification can aid in setting up the search.

Abstract: Methods and systems are provided. In one aspect, a method for parallel extraction of worst case corners of a number of electronic design automation (EDA) simulations includes generating multiple initial EDA simulation results for a number of specifications of an integrated circuit based on a first algorithm. For each specification, a respective first set of input samples is generated based on a second algorithm using generated multiple initial simulation results. Using a third algorithm, two or more of the respective first set of input samples are merged based on a criterion to generate a respective second set of input samples. For each specification, a first set of simulation results is generated using the respective second set of input samples. The worst case corners for the specifications are determined by applying in parallel local optimization to the first set of simulation results.

Abstract: Method for estimating a yield of a post-layout circuit design is provided. In one aspect, a method includes obtaining a first pre-layout parameter and a second pre-layout parameter from pre-layout simulation samples of a circuit. The method also modeling a prior distribution of a first post-layout parameter and a second post-layout parameter based on the first pre-layout parameter, the second pre-layout parameter, a first hyper-parameter, and second hyper-parameter. The method further includes calculating the first hyper-parameter and the second hyper-parameter using a cross-validation, obtaining the first post-layout parameter and the second post-layout parameter based on the first hyper-parameter and the second hyper-parameter and estimating the yield of the circuit design using a non-normal distribution parameterized by the obtained first post-layout parameter and second post-layout parameter.

Abstract: A method for determining mismatch variation of circuit components in a circuit is provided. The method includes determining a mismatch contribution for a specification of an integrated circuit design and displaying a list of components in the circuit design sorted according to the mismatch contribution. The method also includes displaying an adjustable scale for a size of the component, modifying the circuit design according to with the size of the component adjusted according to a user input to the adjustable scale, determining an adjusted mismatch contribution of the component, and displaying in the list of components a modified value of the mismatch contribution, and a modified value of an overall standard deviation for the specification in the circuit design.

Abstract: An improved approach is provided to provide fast access to waveform visualizations for electronic designs. Data reduction is performed on the waveform data, where the quantity of the waveform data is reduced in an intelligent manner, such that the reduced waveform data still retains sufficient data fidelity for accurate data analysis and waveform visualization. The reduced data can then be displayed in an accelerated manner. From the display of the reduced data, this allows the user to select only the specific one or more waveforms for which the user seeks viewing of the full waveform data.

Abstract: A method including separating multiple signal waveforms into multiple blocks forming a sequence is provided. Each of the blocks includes at least a portion of each of the multiple signal waveforms. The method includes identifying a shared time portion and a shared signal portion for the signal waveforms within a first block from the multiple blocks and selecting a format for the first block based on a block size of the first block and a block read time of the first block. The method also includes compressing data in the first block based on the shared time portion, the shared signal portion, a preceding block and a subsequent block in the sequence, and storing the first block in a memory based on the format selected for the first block.

Abstract: A system, method, and computer program product for reducing the number of Monte Carlo simulation samples required to determine if a design meets design specifications. The worst sample for each specification acts as a design corner to substitute for a full design verification. Embodiments determine the maximum number of samples needed, perform an initial performance modeling using an initial set of samples, and estimate the failure probability of each of the remaining samples based on the performance model. Embodiments then simulate remaining samples with a computer-operated Monte Carlo circuit simulation tool in decreasing design specification model accuracy order, wherein the sample predicted most likely to fail each specification is simulated first. Re-use of simulation results progressively improves models. Probability based stop criteria end the simulation early when the worst samples have been confidently found. A potential ten-fold reduction in overall specification verification time may result.

Abstract: A system, method, and computer program product for efficiently finding the best Monte Carlo simulation samples for use as design corners for all design specifications to substitute for a full circuit design verification. Embodiments calculate a corner target value matching an input variation level by modeling the circuit performance with verified accuracy, estimate the corner based on a response surface model such that the corner has the highest probability density (or extrapolation from the worst sample if the model is inaccurate), and verify and/or adjust the corner by performing a small number of additional simulations. Embodiments also estimate the probability that a design already meets the design specifications at a specified variation level. Composite multimodal and non-Gaussian probability distribution functions enhance model accuracy. The extracted design corners may be of particular utility during circuit design iterations.

Abstract: A system, method, and computer program product for automatically reducing the number of Monte Carlo simulation samples required to determine if a design yield is above or below a given yield target with a given confidence. Embodiments perform an initial Monte Carlo based performance modeling using an initial set of statistical samples, and estimate the failure probability of each of the remaining statistical samples based on the performance model. Embodiments then simulate each of the remaining statistical samples with a computer-operated Monte Carlo circuit simulation tool in decreasing failure probability order, wherein the sample most likely to fail is simulated first. Progressive comparisons of the simulated yield against a yield target eventually verify the yield at a required confidence level, halting the simulation and triggering tangible output of the comparison results. A potential ten-fold decrease in overall yield verification time without loss of accuracy may result.

Abstract: A system, method, and computer program product for automatically approximating conventional Monte Carlo statistical device model evaluation for circuit simulation with drastic speed improvements, while preserving significant accuracy. Embodiments enable quick inspection of the effects of process mismatch variations on single devices and even large circuits compared to standard computationally prohibitive Monte Carlo analysis. Statistical device model variation is calculated as if all such variation is due to changes in threshold voltage, even though other physical phenomena are known to contribute. Threshold voltage variation is modeled as a function of statistical variation, device size, and working bias condition. Circuit simulation is faster when the full internal device model parameter set is not rebuilt for every Monte Carlo analysis iteration. Embodiments are compatible with both conventional SPICE and newer Fast SPICE simulations.

Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. When the samples exceed the mismatch parameters, a linear model is solved by least squares. Otherwise, a linear model is solved by orthogonal matching pursuit (OMP), and if that solution is too inaccurate then a new mixed method builds a better linear model. If the linear solution is too inaccurate, a full linear and quadratic model is made using OMP to select the most important variables, and the full model is fitted using OMP with selected cross terms. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions.