Patents by Inventor Hongzhou ZHAO

Hongzhou ZHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12276322
    Abstract: An electromechanical actuator for forced unlocking of a fuzzy jamming fault of a transmission mechanism comprises a bidirectional electromagnetic braking assembly, a circumferential rotating housing assembly, an axial spline bearing assembly, an LVDT linear displacement sensor assembly, a potentiometer linear displacement sensor assembly, and an electromechanical actuator assembly. The axial spline bearing assembly is mounted inside the circumferential rotating housing assembly for a reciprocating linear motion, and the axial spline bearing assembly is connected to an output rotating shaft of the electromechanical actuator assembly to form a spiral transmission pair; the bidirectional electromagnetic braking assembly is actively energized to generate radial and axial attraction forces, so that the circumferential rotating housing assembly is disengaged from a fixed connection with the electromechanical actuator assembly to rotate.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: April 15, 2025
    Assignee: Beijing Institute of Precision Mechatronics and Controls
    Inventors: Hongzhou Song, Zhiyuan Yu, Shoujun Zhao, Zheqing Zuo, Zhe Zhao, Bo Zeng, Zonglun Li, Haiping Zhou, Xiaorong Zhu, Yecheng Yin, Zixing Wang
  • Publication number: 20250104181
    Abstract: Techniques are disclosed relating to data compression in graphics processors. In some embodiments, cache circuitry is coupled to shader processor circuitry and is configured to store graphics data that includes a compressed block of data associated with a surface and metadata for the compressed block of data. Metadata coherence circuitry may cache the metadata for the compressed block of data, receive an indication of a write command for non-compressed data associated with the surface, wherein the write command identifies the metadata and has a different address than the compressed block of data, and determine, based on the metadata and the indication, to invalidate the compressed block of data in the cache circuitry. This may maintain read/write coherence in a cache that stores both compressed and uncompressed data, in some embodiments.
    Type: Application
    Filed: August 6, 2024
    Publication date: March 27, 2025
    Inventors: Karthik Ramani, Tyson J. Bergland, Leela Kishore Kothamasu, Hongzhou Zhao, Winnie W. Yeung, Mladen Wilder
  • Patent number: 9411733
    Abstract: A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term sharing pattern refers to a group of processors accessing a single memory location in an application. The sharing pattern is decoupled from each cache line and held in a separate directory table. The sharing pattern of a cache block is the bit vector representing the processors that share the block. Multiple cache lines that have the same sharing pattern point to a common entry in the directory table. In addition, when the table capacity is exceeded, patterns that are similar to each other are dynamically collated into a single entry.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: August 9, 2016
    Assignee: University of Rochester
    Inventors: Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas
  • Publication number: 20140032848
    Abstract: A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term sharing pattern refers to a group of processors accessing a single memory location in an application. The sharing pattern is decoupled from each cache line and held in a separate directory table. The sharing pattern of a cache block is the bit vector representing the processors that share the block. Multiple cache lines that have the same sharing pattern point to a common entry in the directory table. In addition, when the table capacity is exceeded, patterns that are similar to each other are dynamically collated into a single entry.
    Type: Application
    Filed: September 7, 2012
    Publication date: January 30, 2014
    Applicant: UNIVERSITY OF ROCHESTER
    Inventors: Hongzhou ZHAO, Arrvindh SHRIRAMAN, Sandhya DWARKADAS