Patents by Inventor Honnahuggi Harinath Venkata Naga Ambica Prasad

Honnahuggi Harinath Venkata Naga Ambica Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10817627
    Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. A color is assigned to each HCG node to minimize HoL conflicts. A traffic graph (TG) is constructed for each color based on the physical data, the bridge data, the traffic data and the HCG, and a candidate topology is generated for each color based on the respective TG. The candidate topology for each color is merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Arm Limited
    Inventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan
  • Patent number: 10783286
    Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. A color is assigned to each HCG node to minimize HoL conflicts. A traffic graph (TG) is constructed for each color based on the physical data, the bridge data, the traffic data and the HCG, and a candidate topology is generated for each color based on the respective TG. The candidate topology for each color is merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 22, 2020
    Assignee: Arm Limited
    Inventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan
  • Publication number: 20200134127
    Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node; using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path; using the computer, performing one or more iterations of modifying the integrated circuit topology by: (i) detecting two or more connected groups of the data han
    Type: Application
    Filed: October 25, 2018
    Publication date: April 30, 2020
    Inventors: Anup GANGWAR, Nitin Kumar AGARWAL, Honnahuggi Harinath Venkata Naga Ambica PRASAD
  • Patent number: 10628626
    Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node; using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path; using the computer, performing one or more iterations of modifying the integrated circuit topology by: (i) detecting two or more connected groups of the data han
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 21, 2020
    Assignee: Arm Limited
    Inventors: Anup Gangwar, Nitin Kumar Agarwal, Honnahuggi Harinath Venkata Naga Ambica Prasad