Patents by Inventor Hoo-Seung Cho

Hoo-Seung Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6724052
    Abstract: A semiconductor device includes a substrate of a first conductive type, and a well region of an opposite second conductive type is formed in the substrate. A first impurity region of the first conductive type extends to a first depth within the well region, and a second impurity region of the first conductive type is spaced from the first impurity region to define a channel region therebetween and extends to a second depth within the well region. Preferably, the second depth is greater than the first depth. A gate electrode is located over the channel region, and a silicide layer is formed at a third depth within the first impurity region. The third depth is less than the first depth, and a difference between the first depth and the third depth is less than or equal to a difference at which a leakage current from the silicide layer to the well region is sufficient to electrically bias the well region through the silicide layer.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: April 20, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-Sik Cho, Hoo-Seung Cho, Gyu-Chul Kim, Yong Park, Han-Soo Kim
  • Publication number: 20020179979
    Abstract: A semiconductor device includes a substrate of a first conductive type, and a well region of an opposite second conductive type is formed in the substrate. A first impurity region of the first conductive type extends to a first depth within the well region, and a second impurity region of the first conductive type is spaced from the first impurity region to define a channel region therebetween and extends to a second depth within the well region. Preferably, the second depth is greater than the first depth. A gate electrode is located over the channel region, and a silicide layer is formed at a third depth within the first impurity region. The third depth is less than the first depth, and a difference between the first depth and the third depth is less than or equal to a difference at which a leakage current from the silicide layer to the well region is sufficient to electrically bias the well region through the silicide layer.
    Type: Application
    Filed: July 15, 2002
    Publication date: December 5, 2002
    Inventors: Kang-Sik Cho, Hoo-Seung Cho, Gyu-Chul Kim, Yong Park, Han-Soo Kim