Abstract: A memory device includes a pair of common source lines disposed on a substrate spaced apart from each other and extended in a first direction; a plurality of ground select lines disposed between the pair of common source lines, extended in the first direction, and disposed on the same level; a plurality of word lines disposed on the plurality of ground select lines between the pair of common source lines, extended in the first direction, and disposed on the same level, at least a portion of the plurality of word lines being connected by a connection electrode; and a plurality of first separation insulating patterns disposed between individual ground select lines of a portion of the plurality of ground select lines and extended in the first direction. The at least portion of the plurality of word lines is connected by a connection electrode.

Abstract: A memory device includes a pair of common source lines disposed on a substrate spaced apart from each other and extended in a first direction; a plurality of ground select lines disposed between the pair of common source lines, extended in the first direction, and disposed on the same level; a plurality of word lines disposed on the plurality of ground select lines between the pair of common source lines, extended in the first direction, and disposed on the same level, at least a portion of the plurality of word lines being connected by a connection electrode; and a plurality of first separation insulating patterns disposed between individual ground select lines of a portion of the plurality of ground select lines and extended in the first direction. The at least portion of the plurality of word lines is connected by a connection electrode.

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

Abstract: A memory device includes a pair of common source lines disposed on a substrate spaced apart from each other and extended in a first direction; a plurality of ground select lines disposed between the pair of common source lines, extended in the first direction, and disposed on the same level; a plurality of word lines disposed on the plurality of ground select lines between the pair of common source lines, extended in the first direction, and disposed on the same level, at least a portion of the plurality of word lines being connected by a connection electrode; and a plurality of first separation insulating patterns disposed between individual ground select lines of a portion of the plurality of ground select lines and extended in the first direction. The at least portion of the plurality of word lines is connected by a connection electrode.

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

Abstract: A memory device includes a pair of common source lines disposed on a substrate spaced apart from each other and extended in a first direction; a plurality of ground select lines disposed between the pair of common source lines, extended in the first direction, and disposed on the same level; a plurality of word lines disposed on the plurality of ground select lines between the pair of common source lines, extended in the first direction, and disposed on the same level, at least a portion of the plurality of word lines being connected by a connection electrode; and a plurality of first separation insulating patterns disposed between individual ground select lines of a portion of the plurality of ground select lines and extended in the first direction. The at least portion of the plurality of word lines is connected by a connection electrode.

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

Abstract: A semiconductor device includes a plurality of semiconductor devices, a plurality of metal lines electrically connected to at least one of the semiconductor devices, and a protective layer on the metal lines. The protective layer includes a plurality of open areas partially exposing the metal lines and which serves as pads. A first pad includes a first area that extends from at least one of the metal lines and at least one second area around and separated from the first area.

Abstract: Provided is a semiconductor device. The semiconductor device includes an insulating layer extending in a first direction. A first vertical channel pillar is disposed separately from the insulating layer. A first interconnection line extends in a second direction perpendicular to the first direction, and is electrically connected to the first vertical channel pillar. A first bit line extends in the second direction, and crosses over the first interconnection line and the first vertical channel pillar. A first bit contact overlaps the first interconnection line, and electrically connects the first interconnection line to the first bit line. A length of the first bit contact in the second direction is greater than a length of the first bit contact in the first direction.

Abstract: A fabricating method of a customized mask includes forming first patterns in a mold structure, forming second patterns in the mold structure using initial masks, the mold structure having the first patterns formed therein, measuring overlap failure between the first patterns and the second patterns, and fabricating customized masks by compensating for pattern positions of the initial masks based on the measuring results, wherein compensating for the pattern positions of the initial masks includes shifting positions of at least some patterns of the initial masks according to shift directions and sizes of at least some of the first patterns.

Abstract: Provided is a semiconductor device. The semiconductor device includes an insulating layer extending in a first direction. A first vertical channel pillar is disposed separately from the insulating layer. A first interconnection line extends in a second direction perpendicular to the first direction, and is electrically connected to the first vertical channel pillar. A first bit line extends in the second direction, and crosses over the first interconnection line and the first vertical channel pillar. A first bit contact overlaps the first interconnection line, and electrically connects the first interconnection line to the first bit line. A length of the first bit contact in the second direction is greater than a length of the first bit contact in the first direction.

Abstract: Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the upper wordline in a transverse direction and the lower wordline may include a wiring area exposed by the recessed portion of the upper wordline. The wiring structures may also include an upper contact plug contacting the upper wordline and a lower contact plug contacting the wiring area. The upper and lower contact plugs may extend in a vertical direction.

Abstract: A non-volatile memory device includes a substrate including an active region and a field region, selection transistors and cell transistors on the active region, bit line contacts on the bridge portions, and shared bit lines electrically connected to the bit line contacts. The active region includes string portions and bridge portions. The string portions extend in a first direction and are arranged in a second direction substantially perpendicular to the first direction, and the bridge portions connect at least two adjacent string portions. Each bridge portion has a length in the first direction equal to or longer than about twice a width of each bit line contact in the first direction.

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

Abstract: Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the upper wordline in a transverse direction and the lower wordline may include a wiring area exposed by the recessed portion of the upper wordline. The wiring structures may also include an upper contact plug contacting the upper wordline and a lower contact plug contacting the wiring area. The upper and lower contact plugs may extend in a vertical direction.

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the rings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.