Abstract: A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile semiconductor memory has a memory cell array that includes normal memory cells and a flag memory cell. The flag memory cell is configured to be more susceptible to electrical stress on its retention of data than the normal memory cells. The memory monitors data stored in the flag memory cell to monitor a data retention characteristic of the normal memory cells.

Abstract: Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.

Abstract: Methods of performing multi-block erasing operations on a memory device that includes a plurality of memory blocks are provided. Pursuant to these methods, the rate at which a first voltage that is applied to the memory blocks that are to be erased during the multi-block erasing operation rises is controlled based on the number of memory blocks that are to be erased. The memory device may be a flash memory device, and the first voltage may be an erasing voltage that is applied to a substrate of the flash memory device. The rate at which the first voltage rises may be set so that the substrate of the flash memory device reaches the erasing voltage level at approximately the same time regardless of the number of memory blocks that are to be erased.

Abstract: A liquid crystal display device, and a fabricating method thereof, that is capable of providing uniform liquid cell gaps. A main seal defines a liquid crystal injection area. A first step coverage-compensating layer is provided between a substrate on which the main seal has been coated and the main seal. A plurality of dummy seals is arranged external to the main seal. A second step coverage-compensating layer having the same thickness as the first step coverage-compensating layer is provided between the substrate on which the dummy seals are arranged and the dummy seals. Accordingly, a main seal and dummy seals having the same thickness produce uniform liquid crystal cell gaps. The liquid crystal display device is beneficially made by a fabrication process employing four or five masks.

Abstract: Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.

Abstract: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

Abstract: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

Abstract: A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile semiconductor memory has a memory cell array that includes normal memory cells and a flag memory cell. The flag memory cell is configured to be more susceptible to electrical stress on its retention of data than the normal memory cells. The memory monitors data stored in the flag memory cell to monitor a data retention characteristic of the normal memory cells.

Abstract: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

Abstract: Methods of performing multi-block erasing operations on a memory device that includes a plurality of memory blocks are provided. Pursuant to these methods, the rate at which a first voltage that is applied to the memory blocks that are to be erased during the multi-block erasing operation rises is controlled based on the number of memory blocks that are to be erased. The memory device may be a flash memory device, and the first voltage may be an erasing voltage that is applied to a substrate of the flash memory device. The rate at which the first voltage rises may be set so that the substrate of the flash memory device reaches the erasing voltage level at approximately the same time regardless of the number of memory blocks that are to be erased.

Abstract: A liquid crystal display device, and a fabricating method thereof, that is capable of providing uniform liquid cell gaps. A main seal defines a liquid crystal injection area. A first step coverage-compensating layer is provided between a substrate on which the main seal has been coated and the main seal. A plurality of dummy seals is arranged external to the main seal. A second step coverage-compensating layer having the same thickness as the first step coverage-compensating layer is provided between the substrate on which the dummy seals are arranged and the dummy seals. Accordingly, a main seal and dummy seals having the same thickness produce uniform liquid crystal cell gaps. The liquid crystal display device is beneficially made by a fabrication process employing four or five masks.

Abstract: According to embodiments of the invention, during a test operation a semiconductor device where an overcurrent flows is detected from among a plurality of semiconductor devices formed on the semiconductor wafer. The power to the semiconductor device where the overcurrent flows may be automatically cut. Furthermore, an overcurrent detection result with respect to semiconductor devices disposed on the wafer is provided to a test apparatus.

Abstract: An electrostatic damage preventing apparatus for a thin film transistor array of a liquid crystal display includes a horizontal ground voltage line disposed at a first perimeter portion of the thin film transistor array, a vertical ground voltage line disposed at a second perimeter portion of the thin film transistor array, and a first electrostatic damage-preventing switching device group including parallel connection of at least two electrostatic damage-preventing switching devices to divide and divert an electrostatic voltage applied over the horizontal ground voltage line.

Abstract: A liquid crystal display device, and a fabricating method thereof, that is capable of providing uniform liquid cell gaps. A main seal defines a liquid crystal injection area. A first step coverage-compensating layer is provided between a substrate on which the main seal has been coated and the main seal. A plurality of dummy seals is arranged external to the main seal. A second step coverage-compensating layer having the same thickness as the first step coverage-compensating layer is provided between the substrate on which the dummy seals are arranged and the dummy seals. Accordingly, a main seal and dummy seals having the same thickness produce uniform liquid crystal cell gaps. The liquid crystal display device is beneficially made by a fabrication process employing four or five masks.

Abstract: An electrostatic damage preventing apparatus for a thin film transistor array of a liquid crystal display includes a horizontal ground voltage line disposed at a first perimeter portion of the thin film transistor array, a vertical ground voltage line disposed at a second perimeter portion of the thin film transistor array, and a first electrostatic damage-preventing switching device group including parallel connection of at least two electrostatic damage-preventing switching devices to divide and divert an electrostatic voltage applied over the horizontal ground voltage line.