Patents by Inventor Hooi Kar Loo
Hooi Kar Loo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11533170Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.Type: GrantFiled: March 28, 2019Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Reouven Elbaz, Hooi Kar Loo, Poh Thiam Teoh, Su Wei Lim, Patrick D. Maloney, Santosh Ghosh
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Publication number: 20210382839Abstract: Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.Type: ApplicationFiled: August 25, 2021Publication date: December 9, 2021Applicant: Intel CorporationInventors: Christopher Wing Hong Ngau, Hooi Kar Loo, Poh Thiam Teoh, Shashitheren Kerisnan, Maxim Dan, Chee Siang Chow
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Patent number: 11132319Abstract: Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.Type: GrantFiled: January 12, 2018Date of Patent: September 28, 2021Assignee: Intel CorporationInventors: Christopher Wing Hong Ngau, Hooi Kar Loo, Poh Thiam Teoh, Shashitheren Kerisnan, Maxim Dan, Chee Siang Chow
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Method, apparatus, and system for power management on a CPU die via clock request messaging protocol
Patent number: 11016549Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.Type: GrantFiled: January 12, 2018Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Poh Thiam Teoh, Mikal C. Hunsaker, Su Wei Lim, Gim Chong Lee, Hooi Kar Loo, Shashitheren Kerisnan, Siang Lin Tan, Ming Chew Lee, Ngeok Kuan Wai, Li Len Lim -
Patent number: 10664433Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.Type: GrantFiled: June 30, 2016Date of Patent: May 26, 2020Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Timothy J. Callahan, Hem Doshi, Hooi Kar Loo, Suketu U. Bhatt
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Patent number: 10657092Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.Type: GrantFiled: June 30, 2016Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Timothy J. Callahan, Hem Doshi, Hooi Kar Loo, Suketu U. Bhatt
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Publication number: 20190229901Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.Type: ApplicationFiled: March 28, 2019Publication date: July 25, 2019Applicant: Intel CorporationInventors: Reouven Elbaz, Hooi Kar Loo, Poh Thiam Teoh, Su Wei Lim, Patrick D. Maloney, Santosh Ghosh
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Patent number: 10257825Abstract: Aspects of the embodiments are directed to systems, methods, and devices, such as an upstream device that includes an input/output port. The input/output port configured to receive a message from an output port of a downstream device; transmit a plurality of acknowledgement messages to the downstream device; and transmit a response message to the received message to the downstream device.Type: GrantFiled: September 30, 2016Date of Patent: April 9, 2019Assignee: Intel CorporationInventors: Say Cheong Gan, Poh Thiam Teoh, Hooi Kar Loo, Sun Zheng E, Keng Dar Ang
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Patent number: 10229080Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.Type: GrantFiled: July 17, 2015Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Ting Lok Song, Su Wei Lim, Mikal C. Hunsaker, Hooi Kar Loo
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Publication number: 20190042510Abstract: Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.Type: ApplicationFiled: January 12, 2018Publication date: February 7, 2019Inventors: Christopher Wing Hong Ngau, Hooi Kar Loo, Poh Thiam Teoh, Shashitheren Kerisnan, Maxim Dan, Chee Siang Chow
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METHOD, APPARATUS, AND SYSTEM FOR POWER MANAGEMENT ON A CPU DIE VIA CLOCK REQUEST MESSAGING PROTOCOL
Publication number: 20190041936Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.Type: ApplicationFiled: January 12, 2018Publication date: February 7, 2019Inventors: Poh Thiam Teoh, Mikal C. Hunsaker, Su Wei Lim, Gim Chong Lee, Hooi Kar Loo, Shashitheren Kerisnan, Siang Lin Tan, Ming Chew Lee, Ngeok Kuan Wai, Li Len Lim -
Publication number: 20180004702Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: LAKSHMINARAYANA PAPPU, TIMOTHY J. CALLAHAN, HEM DOSHI, HOOI KAR LOO, SUKETU U. BHATT
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Publication number: 20180004701Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: LAKSHMINARAYANA PAPPU, TIMOTHY J. CALLAHAN, HEM DOSHI, HOOI KAR LOO, SUKETU U. BHATT
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Patent number: 9558030Abstract: Methods, apparatuses, and systems for handling transactions received after a configuration request, the method, for example, comprising: receiving a configuration change request by a transaction-handling logic block; performing a configuration change by the transaction-handling logic block in response to the configuration change request, wherein the logic block is to handle transactions received prior to receipt of the configuration change request differently than transactions received after receipt of the configuration change request; receiving, by the transaction-handling logic block, a first transaction before receiving the configuration change request; receiving, by the transaction-handling logic block, a second transaction after receiving the configuration change request and before the configuration change is complete; differentiating the first transaction from the second transaction based on the order in which the first and second transactions were received relative to receipt of the configuration changType: GrantFiled: November 9, 2011Date of Patent: January 31, 2017Assignee: Intel CorporationInventors: Su Wei Lim, Kah Meng Yeem, Poh Thiam Teoh, Hooi Kar Loo, Sujea Lim
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Publication number: 20160085707Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.Type: ApplicationFiled: July 17, 2015Publication date: March 24, 2016Inventors: Ting Lok Song, Su Wei Lim, Mikal C. Hunsaker, Hooi Kar Loo
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Patent number: 9124455Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.Type: GrantFiled: September 24, 2014Date of Patent: September 1, 2015Assignee: Intel CorporationInventors: Su Wei Lim, Ronald W. Swartz, Yueming Jiang, Hooi Kar Loo, Athourina Gevergiz, Bruce A. Tennant, Yick Yaw Ho, Poh Thiam Teoh, Jennifer Chin, Hui Shi
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Patent number: 9098642Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.Type: GrantFiled: March 3, 2014Date of Patent: August 4, 2015Assignee: Intel CorporationInventors: Ting Lok Song, Su Wei Lim, Mikal C. Hunsaker, Hooi Kar Loo
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Publication number: 20140181356Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.Type: ApplicationFiled: March 3, 2014Publication date: June 26, 2014Inventors: Ting Lok Song, Su Wei Lim, Mikal Hunsaker, Hooi Kar Loo
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Patent number: 8706944Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.Type: GrantFiled: December 22, 2010Date of Patent: April 22, 2014Assignee: Intel CorporationInventors: Ting Lok Song, Su Wei Lim, Mikal Hunsaker, Hooi Kar Loo
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Publication number: 20130275985Abstract: Methods, apparatuses, and systems for handling transactions received after a configuration request, the method, for example, comprising: receiving a configuration change request by a transaction-handling logic block; performing a configuration change by the transaction-handling logic block in response to the configuration change request, wherein the logic block is to handle transactions received prior to receipt of the configuration change request differently than transactions received after receipt of the configuration change request; receiving, by the transaction-handling logic block, a first transaction before receiving the configuration change request; receiving, by the transaction-handling logic block, a second transaction after receiving the configuration change request and before the configuration change is complete; differentiating the first transaction from the second transaction based on the order in which the first and second transactions were received relative to receipt of the configuration changType: ApplicationFiled: November 9, 2011Publication date: October 17, 2013Applicant: INTEL CORPORATIONInventors: Su Wei Lim, Kah Meng Yeem, Poh Thiam Teoh, Hooi Kar Loo, Sujea Lim