Patents by Inventor Hoon Jang

Hoon Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9875038
    Abstract: A storage device including a nonvolatile memory device is provided. The storage device may include: a nonvolatile memory device; and a controller configured to control a read operation of the nonvolatile memory device according to a read request from an external host device. The controller is configured to read map data including a segment, and to store different types of map data in an internal random access memory (RAM) based on determining whether the segment corresponds to sequential data.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Hoon Jang, Bomi Kim, Songho Yoon
  • Publication number: 20180019257
    Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.
    Type: Application
    Filed: April 7, 2017
    Publication date: January 18, 2018
    Inventors: Young Hwan SON, Won Chul JANG, Dong Seog EUN, Jae Hoon JANG
  • Publication number: 20180017713
    Abstract: Disclosed herein is an anti-reflective film comprising: a hard coating layer; and a low-refractive layer containing a binder resin and hollow inorganic nanoparticles and solid inorganic nanoparticles which are dispersed in the binder resin, wherein a ratio of an average particle diameter of the solid inorganic nanoparticles to an average particle diameter of the hollow inorganic nanoparticles is 0.26 to 0.
    Type: Application
    Filed: August 3, 2017
    Publication date: January 18, 2018
    Inventors: Jin Seok BYUN, Jae Young KIM, Yeong Rae CHANG, Boo Kyung KIM, Seok Hoon JANG
  • Patent number: 9865390
    Abstract: A coil component includes a first coil part including a multilayer substrate on which a conductor pattern is formed, a second coil part formed as a wire and stacked together with the first coil part, a core coupled to the first and second coil parts while penetrating through the first and second coil parts to thereby be electromagnetically coupled to the first and second coil parts, and a pressing member interposed between the core and the second coil part to allow the first and second coil parts to closely adhere to each other.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: January 9, 2018
    Assignee: Solum Co., Ltd.
    Inventors: Xin Lan Li, Jae Gen Eom, Geun Young Park, Se Hoon Jang, Heung Gyoon Choi
  • Publication number: 20180002505
    Abstract: Provided herein is a composition of a polypropylene resin with improved foaming capability with improved foaming capability, such as a polypropylene comprising a foaming agent master batch and a highly flowable polypropylene resin having non-controlled rheology. The resin composition exhibits excellent foaming quality and can be easily injected. The polypropylene resin with improved foaming capability comprises a mixture comprising from about 50% to about 80% by weight of a polypropylene resin having a mean molecular weight of about 45,000 g/mol to about 180,000 g/mol, from about 15% to about 30% by weight of a fiber reinforcing agent, and from about 2% to about 20% by weight of a foaming agent.
    Type: Application
    Filed: November 30, 2016
    Publication date: January 4, 2018
    Applicants: Hyundai Motor Company, LOTTE CHEMICAL CORPORATION
    Inventors: Boo-Youn AN, Dae-Sik KIM, In-Soo HAN, Kyeong-Hoon JANG, Seul YI, Seong-Min JO, Eun-Hwa JANG, Yeong-Beom KIM
  • Publication number: 20170373089
    Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.
    Type: Application
    Filed: December 29, 2016
    Publication date: December 28, 2017
    Inventors: Kwang Soo KIM, Shin Hwan KANG, Jae Hoon JANG, Kohji KANAMORI
  • Patent number: 9853049
    Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of channel areas passing through the gate structure and extending in a direction perpendicular to the upper surface of the substrate, a source area disposed on the substrate to extend in a first direction and including impurities, and a common source line extending in the direction perpendicular to the upper surface of the substrate to be connected to the source area, and including a plurality of layers containing different materials.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: December 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Soo Kim, Jae Hoon Jang, Byoung Keun Son
  • Publication number: 20170365616
    Abstract: A vertical non-volatile memory device includes a substrate including a cell region; a lower insulating layer on the substrate; a lower wiring pattern in the cell region having a predetermined pattern and connected to the substrate through the lower insulating layer; and a plurality of vertical channel layers extending in a vertical direction with respect to a top surface of the substrate in the cell region, spaced apart from one another in a horizontal direction with respect to the top surface of the substrate, and electrically connected to the lower wiring pattern. The memory device also includes a plurality of gate electrodes stacked alternately with interlayer insulating layers in the cell region in the vertical direction along a side wall of a vertical channel layer and formed to extend in a first direction along the horizontal direction.
    Type: Application
    Filed: April 12, 2017
    Publication date: December 21, 2017
    Inventors: Shin-hwan KANG, Heon-kyu LEE, Kohji KANAMORI, Jae-duk LEE, Jae-hoon JANG, Kwang-soo KIM
  • Publication number: 20170358590
    Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.
    Type: Application
    Filed: November 8, 2016
    Publication date: December 14, 2017
    Inventors: Shin-hwan KANG, Young-hwan SON, Dong-seog EUN, Chang-sup LEE, Jae-hoon JANG
  • Publication number: 20170343704
    Abstract: The present invention relates to a low refractive layer and an anti-reflective film comprising the same. The low refractive layer can exhibit excellent optical properties such as a low reflectance and a high light transmittance, and excellent mechanical properties such as high wear resistance and scratch resistance at the same time, without adversely affecting the color of the polymer resin forming the low refractive layer. In particular, due to the excellent alkali resistance, the low refractive layer can maintain excellent physical properties even after alkali treatment. Therefore, when introducing a low refractive layer to the display device, it is expected that the production process can be simplified and further the production rate and the productivity can significantly increase.
    Type: Application
    Filed: June 30, 2017
    Publication date: November 30, 2017
    Inventors: Boo Kyung KIM, Yeong Rae CHANG, Seok Hoon JANG, Eun Kyu HER, Jin Seok BYUN
  • Publication number: 20170340502
    Abstract: Disclosed is a rehabilitation training apparatus including a pair of first tracks that are arranged in parallel at an interval, a second track that is perpendicular to the pair of first tracks and is movably connected to the pair of first tracks, a hand holder that is movably provided in the second track and on which a hand of the user is held, a holder driving unit that reciprocally moves the hand holder along the second track, and a track driving unit that reciprocally moves the second track along the pair of first tracks.
    Type: Application
    Filed: October 12, 2016
    Publication date: November 30, 2017
    Inventors: Sung Jun ROH, Hyun Soo KIM, Soo Bin LEE, Ho Yeong SONG, Ho Young BAN, Young Geun CHOI, Dae Hoon JANG, Byeong Geol PARK
  • Publication number: 20170345823
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory may include a semiconductor substrate having an isolation trench in a first region and a capacitor trench in a second region, an isolation layer filling the isolation trench, an insulation layer pattern disposed along the capacitor trench, and a conductive layer pattern filling the capacitor trench over the insulation layer pattern. A capacitor includes a first portion of the semiconductor substrate in the second region, the insulation layer pattern, and the conductive pattern. A sidewall of the capacitor trench has a first angle with respect to a surface of the semiconductor substrate and a sidewall of the isolation trench has a second angle with respect to the surface of the semiconductor substrate. The first angle is more proximate to 90 degrees than the second angle.
    Type: Application
    Filed: January 26, 2017
    Publication date: November 30, 2017
    Inventor: Bong-Hoon JANG
  • Patent number: 9824810
    Abstract: A transformer includes a magnetic core, a first coil unit and a second coil unit. The first coil unit is disposed within the magnetic core and includes a laminated board having layers laminated therein and conductive patterns. Respective ones of the conductive patterns are disposed on the laminated layers. The second coil unit includes a conductive wire spaced apart from the conductive patterns of the laminated board by an insulating distance. The conductive wire includes a triple-insulated wire surrounded by three sheets of insulating paper to maintain the insulating distance from the conductive patterns.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 21, 2017
    Assignee: SOLUM CO., LTD.
    Inventors: Jae Gen Eom, Young Seung Noh, Heung Gyoon Choi, Geun Young Park, Sung Yun Han, Seh Hoon Jang, Nak Jun Jeong, Young Min Lee, Jong Woo Kim, Tae Won Heo
  • Patent number: 9825453
    Abstract: A protection mode control circuit includes an auto-restart counter configured to count the cycle of a first signal in a protection condition and to generate an auto-restart signal when a result of the count reaches a protection reference value and a latch mode unit configured to generate a latch mode signal for changing protection mode to latch mode when the auto-restart signal is consecutively generated by a predetermined threshold number.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: November 21, 2017
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Won-Tae Lee, Ji-Hoon Jang, Hyeong Seok Baek, Hang-Seok Choi
  • Publication number: 20170330632
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Inventors: Sun-Il SHIM, Jae-Hoon JANG, Donghyuk CHAE, Youngho LIM, Hansoo KIM, Jaehun JEONG
  • Patent number: 9812855
    Abstract: A resonant converter includes a first switch on the primary side and a second switch coupled to the first switch, a synchronization rectification switch on a secondary side configured to conduct during a conduction period in response to a switching operation of the first switch, and a switch control circuit configured to determine an operating region of the resonant converter to be below resonance based on a result of a comparison between the conduction period and an on period of the first switch.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: November 7, 2017
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Won-Tae Lee, Ji-Hoon Jang, Hyeong Seok Baek, Hang-Seok Choi
  • Patent number: 9809691
    Abstract: A polyolefin composite composition is used in an automotive air duct. The polyolefin composite composition is useful as an automotive air duct component material due to excellent mechanical property, heat resistance, and foaming property as a composition in which a polyethylene resin and a long chain branched polypropylene resin having low crystallization of 45% or less are included as a base resin.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: November 7, 2017
    Assignees: Hyundai Motor Company, Lotte Chemical Corporation, Kia Motors Corporation
    Inventors: Seul Yi, Boo Youn An, Dae Sik Kim, Kyeong Hoon Jang, In Soo Han, You Jin Park, Byung Kook Nam, Hyeung Shin Lee, Hyun Jin Kim
  • Patent number: 9812856
    Abstract: A modulation mode control circuit includes a modulation mode controller configured to select modulation mode based on the result of a comparison between a control voltage and a predetermined PWM threshold voltage and to generate a PWM reference voltage using the PWM threshold voltage and the control voltage and a control signal generation unit configured to generate a first control signal based on the result of a comparison between an oscillation control signal for controlling a switching frequency and the control voltage and the result of a comparison between the oscillation control signal and the PWM threshold voltage and to generate a second control signal based on the result of a comparison between the oscillation control signal and the PWM reference voltage.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: November 7, 2017
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Won-Tae Lee, Ji-Hoon Jang, Hyeong Seok Baek
  • Patent number: 9811750
    Abstract: A character input method using a touch screen, in which one or more areas requiring user input is defined in the touch screen, pre-recognized information is defined for each of the defined areas, character information is received by a user in one or more user desired areas among the defined areas, the character information is recognized using a character recognizer, and the recognized character information is updated in the user desired areas.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 7, 2017
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Do-Hyeon Kim, Seong-Taek Hwang, Hee-Bum Ahn, Dong-Hoon Jang, Mu-Sik Kwon, Sang-Wook Oh, Jeong-Wan Park
  • Publication number: 20170309635
    Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of channel areas passing through the gate structure and extending in a direction perpendicular to the upper surface of the substrate, a source area disposed on the substrate to extend in a first direction and including impurities, and a common source line extending in the direction perpendicular to the upper surface of the substrate to be connected to the source area, and including a plurality of layers containing different materials.
    Type: Application
    Filed: August 19, 2016
    Publication date: October 26, 2017
    Inventors: Kwang Soo Kim, Jae Hoon JANG, Byoung Keun SON