Abstract: Manufacturing yield loss of NAND Flash dies is reduced by selecting a plane to store a read-only reserved block and another plane to store a backup read-only reserved block based on the Number of Valid Blocks (NVB) blocks in each plane in the NAND Flash array.

Abstract: Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.

Abstract: Systems, apparatuses, and methods may provide for technology that arranges a wordline access structure for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a plurality of wordlines penetrating through a plurality of decks of a non-volatile memory structure. A plurality of through array vias penetrate through the plurality of decks, where the plurality of through array vias and the plurality of wordlines are comingled in a shared wordline access structure area. Additionally, or alternatively, the memory device is manufactured based on forming multi-level via holes penetrating through a plurality of decks of a non-volatile memory structure of a memory device based on wordline contact patterning. A metal film is deposited to fill the via holes to form wordline contacts.

Abstract: Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.

Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

Abstract: Methods and apparatus for pillar bending improvement by cut tiers pattern implementation. The method uses a cut tier pattern in a staircase region of a 3D memory structure to reduce pillar bending in a pillar array region. The pillar array region includes a plurality of memory tiers comprising wordline layers interposed between isolation layers, where a memory tier comprises a two-dimensional (2D) array of memory cells. A plurality of vertical structures comprising pillars pass through memory cells in the wordline layers and pass through the isolation layers. The staircase structure is disposed adjacent to the pillar array region and includes vertical wordline drivers coupled to the wordline layers. A cut tier pattern comprising vertical trenches is formed in the staircase structure toward a side of the staircase structure adjacent to the pillar array region. The cut tier pattern includes one or more breaks used for routing circuitry in the wordlines.

Abstract: Manufacturing yield loss of NAND Flash dies is reduced by selecting a plane to store a read-only reserved block and another plane to store a backup read-only reserved block based on the Number of Valid Blocks (NVB) blocks in each plane in the NAND Flash array.

Abstract: Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.

Abstract: An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.