Abstract: A semiconductor device includes: a substrate including an upper side and a lower side; first and second active patterns spaced apart from each other; a field insulating film covering side walls of the first and second active patterns; a power rail disposed adjacent to a first side wall of the second active pattern and between the first active pattern and the second active pattern; a power rail via disposed on the power rail and connected to the power rail; a semiconductor etching stop pattern disposed adjacent to a second side wall of the second active pattern; and a first semiconductor pattern disposed on the semiconductor etching stop pattern, wherein a lower surface of the semiconductor etching stop pattern is disposed on substantially a same plane as the lower side of the substrate, and wherein at least part of the first semiconductor pattern is disposed in the field insulating film.

Abstract: A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.

Abstract: A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.