Abstract: A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.

Abstract: A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.

Abstract: Disclosed is a decoder capable of saving power consumption. The decoder according to the present invention is capable of reducing power consumption without a chip area increase which is caused by the modification of an inverter. The decoder in a semiconductor device comprising NAND gates receiving addresses, BiCMOS inverters for inverting outputs from the NAND gates, a clock generator for providing a clock signal for the NAND gates, to control outputs from the BiCMOS inverters in response to the clock signal. Particularly, the decoder according to the present invention reduces power consumption in a stand-by state.

Abstract: The present invention provides an SRAM device comprising a first discharger for discharging a first bit line at the write operation when the first bit line is at a low level; a second discharger for discharging a second bit line at the write operation when the second bit line is at a low level; and a pull-up transistor for providing power with the first and second bit lines at the read operation and preventing the power supply from being provided with the first and second bit lines at the write operation, whereby the first or second dischargers converts the voltage level in low level bit line into a ground level when the write operation is performed.