Patents by Inventor HOON-SEOK SEO
HOON-SEOK SEO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087956Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Inventors: Woojin LEE, Hoon Seok SEO, Sanghoon AHN, Kyu-Hee HAN
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Patent number: 11876017Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.Type: GrantFiled: December 15, 2021Date of Patent: January 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Tae Yong Bae, Hoon Seok Seo, Ki Hyun Park, Hak-Sun Lee
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Patent number: 11823952Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.Type: GrantFiled: December 13, 2022Date of Patent: November 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woojin Lee, Hoon Seok Seo, Sanghoon Ahn, Kyu-Hee Han
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Publication number: 20230114920Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Inventors: Woojin LEE, Hoon Seok SEO, Sanghoon AHN, Kyu-Hee HAN
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Patent number: 11600569Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: GrantFiled: April 14, 2021Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
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Patent number: 11569128Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.Type: GrantFiled: February 12, 2021Date of Patent: January 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woojin Lee, Hoon Seok Seo, Sanghoon Ahn, Kyu-Hee Han
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Publication number: 20220108920Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.Type: ApplicationFiled: December 15, 2021Publication date: April 7, 2022Inventors: Tae Yong Bae, Hoon Seok Seo, Ki Hyun Park, Hak-Sun Lee
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Patent number: 11232986Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.Type: GrantFiled: February 10, 2020Date of Patent: January 25, 2022Inventors: Tae Yong Bae, Hoon Seok Seo, Ki Hyun Park, Hak-Sun Lee
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Publication number: 20210233860Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: ApplicationFiled: April 14, 2021Publication date: July 29, 2021Inventors: SU-HYUN BARK, SANG-HOON AHN, YOUNG-BAE KIM, HYEOK-SANG OH, WOO-JIN LEE, HOON-SEOK SEO, SUNG-JIN KANG
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Patent number: 11049810Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: GrantFiled: June 21, 2019Date of Patent: June 29, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
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Patent number: 11037872Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.Type: GrantFiled: April 4, 2019Date of Patent: June 15, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-Hee Han, Jong-Min Baek, Hoon-Seok Seo, Sang-Hoon Ahn, Woo-Jin Lee
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Publication number: 20210166974Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.Type: ApplicationFiled: February 12, 2021Publication date: June 3, 2021Inventors: Woojin LEE, Hoon Seok SEO, Sanghoon AHN, Kyu-Hee HAN
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Publication number: 20210111070Abstract: Integrated circuit devices and methods of forming the same are provided. The methods of forming an integrated circuit device may include forming a first insulating layer and a via contact on a substrate. The substrate may include an upper surface facing the via contact, and the via contact may be in the first insulating layer and may include a lower surface facing the substrate and an upper surface opposite to the lower surface. The methods may also include forming a second insulating layer and a metallic wire on the via contact. The metallic wire may be in the second insulating layer and may include a lower surface that faces the substrate and contacts the upper surface of the via contact. Both the lower surface of the metallic wire and an interface between the metallic wire and the via contact may have a first width in a horizontal direction that is parallel to the upper surface of the substrate.Type: ApplicationFiled: February 10, 2020Publication date: April 15, 2021Inventors: Tae Yong BAE, Hoon Seok SEO, Ki Hyun PARK, Hak-Sun LEE
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Patent number: 10943824Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.Type: GrantFiled: May 14, 2019Date of Patent: March 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woojin Lee, Hoon Seok Seo, Sanghoon Ahn, Kyu-Hee Han
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Patent number: 10916437Abstract: Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.Type: GrantFiled: December 27, 2018Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Shin Jang, Jong-Min Baek, Hoon-Seok Seo, Eui-Bok Lee, Sung-Jin Kang, Vietha Nguyen, Deok-Young Jung, Sang-Hoon Ahn, Hyeok-Sang Oh, Woo-Kyung You
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Publication number: 20200105664Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a substrate; a first insulating interlayer on the substrate; a first wiring in the first insulating interlayer on the substrate; an insulation pattern on a portion of the first insulating interlayer adjacent to the first wiring, the insulation pattern having a vertical sidewall and including a low dielectric material; an etch stop structure on the first wiring and the insulation pattern; a second insulating interlayer on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.Type: ApplicationFiled: April 4, 2019Publication date: April 2, 2020Inventors: Kyu-Hee HAN, Jong-Min BAEK, Hoon-Seok SEO, Sang-Hoon AHN, Woo-Jin LEE
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Publication number: 20200098620Abstract: A semiconductor device includes a substrate including an active pattern, a first interlayer dielectric layer on the substrate, the first interlayer dielectric layer including a recess on an upper portion thereof, and a lower connection line in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern, the recess of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a barrier pattern between the conductive pattern and the first interlayer dielectric layer, the first interlayer dielectric layer covering a top surface of the barrier pattern.Type: ApplicationFiled: May 14, 2019Publication date: March 26, 2020Inventors: Woojin LEE, Hoon Seok SEO, Sanghoon AHN, Kyu-Hee HAN
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Patent number: 10535600Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.Type: GrantFiled: May 23, 2018Date of Patent: January 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoon Seok Seo, Jong Min Baek, Su Hyun Bark, Sang Hoon Ahn, Hyeok Sang Oh, Eui Bok Lee
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Patent number: 10497649Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: GrantFiled: December 5, 2017Date of Patent: December 3, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang
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Publication number: 20190311992Abstract: An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.Type: ApplicationFiled: June 21, 2019Publication date: October 10, 2019Inventors: Su-Hyun Bark, Sang-Hoon Ahn, Young-Bae Kim, Hyeok-Sang Oh, Woo-Jin Lee, Hoon-Seok Seo, Sung-Jin Kang