Patents by Inventor Hoon SIN
Hoon SIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11557332Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.Type: GrantFiled: May 17, 2021Date of Patent: January 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
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Publication number: 20220332976Abstract: The present application relates to a film. The present application can provide a film having excellent optical characteristics such as transparency or haze, mechanical properties such as hardness, and flexibility, wherein the shape of the surface is controlled to be suitable for various uses, and the controlled surface shape has excellent durability.Type: ApplicationFiled: December 18, 2020Publication date: October 20, 2022Applicant: LG CHEM, LTD.Inventors: Hyun Taek OH, Kwang Seung PARK, Chang Hoon SIN
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Publication number: 20210380463Abstract: The present application relates to a silica glass film. The present application can provide, as a film having a silica network as a main component, a silica glass film capable of solving the disadvantages of the glass material, while having at least one or more advantages of the glass material. Such a silica glass film of the present application can be easily formed through a simple low temperature process without using expensive equipment.Type: ApplicationFiled: November 19, 2019Publication date: December 9, 2021Applicant: LG CHEM, LTD.Inventors: Kwang Seung PARK, Hyun Taek OH, Chang Hoon SIN, Moon Soo PARK
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Publication number: 20210380772Abstract: The present application relates to a glass-like film. The present application can provide a glass-like film capable of solving the disadvantages of the glass material, while having at least one or more advantages of the glass material. Such a glass-like film of the present application can be easily formed through a simple low temperature process without using expensive equipment.Type: ApplicationFiled: November 19, 2019Publication date: December 9, 2021Applicant: LG CHEM, LTD.Inventors: Chang Hoon SIN, Kwang Seung PARK, Hyun Taek OH, Moon Soo PARK
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Publication number: 20210309883Abstract: The present application relates to an optical laminate. The present application can provide an optical laminate having excellent surface properties such as scratch resistance or hardness, which comprises, for example, a cover layer capable of replacing a so-called cover glass.Type: ApplicationFiled: November 19, 2019Publication date: October 7, 2021Applicant: LG CHEM, LTD.Inventors: Kwang Seung PARK, Chang Hoon SIN, Hyun Taek OH, Moon Soo PARK
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Publication number: 20210272623Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Inventors: Sang-Uhn CHA, Hyun-Gi KIM, Hoon SIN, Ye-Sin RYU, In-Woo JUN
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Publication number: 20210178426Abstract: Provided is a method for preparing a silica layer, comprising bringing to gelation a precursor layer formed from a precursor composition comprising a silica precursor an acid catalyst and a surfactant.Type: ApplicationFiled: December 21, 2018Publication date: June 17, 2021Inventors: Hyun Taek OH, Chang Hoon SIN, Kwang Seung PARK, Moon Soo PARK
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Patent number: 11031065Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.Type: GrantFiled: September 17, 2020Date of Patent: June 8, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
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Publication number: 20210005247Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.Type: ApplicationFiled: September 17, 2020Publication date: January 7, 2021Inventors: Sang-Uhn CHA, Hyun-Gi KIM, Hoon SIN, Ye-Sin RYU, In-Woo JUN
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Patent number: 10811078Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.Type: GrantFiled: January 31, 2020Date of Patent: October 20, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
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Publication number: 20200168269Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.Type: ApplicationFiled: January 31, 2020Publication date: May 28, 2020Inventors: Sang-Uhn CHA, Hyun-Gi KIM, Hoon SIN, Ye-Sin RYU, In-Woo JUN
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Patent number: 10586584Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.Type: GrantFiled: December 20, 2018Date of Patent: March 10, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Uhn Cha, Hyun-Gi Kim, Hoon Sin, Ye-Sin Ryu, In-Woo Jun
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Publication number: 20190371391Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.Type: ApplicationFiled: December 20, 2018Publication date: December 5, 2019Inventors: Sang-Uhn CHA, Hyun-Gi KIM, Hoon SIN, Ye-Sin RYU, In-Woo JUN
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Patent number: 10497422Abstract: A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.Type: GrantFiled: January 12, 2018Date of Patent: December 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-jun Lee, Seung-jun Shin, Hoon Sin, Ik-joon Choi, Ju-seong Hwang
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Patent number: 10404286Abstract: A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.Type: GrantFiled: July 31, 2017Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon Sin, Sang-Uhn Cha, Ye-Sin Ryu, Seong-Jin Cho
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Publication number: 20180342283Abstract: A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.Type: ApplicationFiled: January 12, 2018Publication date: November 29, 2018Inventors: Seung-jun LEE, Seung-jun SHIN, Hoon SIN, Ik-joon CHOI, Ju-seong HWANG
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Publication number: 20180152206Abstract: A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.Type: ApplicationFiled: July 31, 2017Publication date: May 31, 2018Inventors: Hoon SIN, Sang-Uhn CHA, Ye-Sin RYU, Seong-Jin CHO
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Patent number: 9628460Abstract: A novel method of dealing with the problem of phishing, pharming, key-logging and man-in-the-middle attacks on internet-based applications which require the submission of valid login credentials, by permitting a user to control access to an internet-based application (3) (such as an internet banking website) by the simple transmission of a command via the internet to allow access to the internet-based application (3) whenever the user wishes to access the application, and by transmitting a command via the internet to deny access to the internet-based application at all other times, to prevent unauthorized access by any unscrupulous parties.Type: GrantFiled: February 16, 2012Date of Patent: April 18, 2017Assignee: E-LOCK CORPORATION SDN. BHD.Inventors: Chik Weng Leong, Chee Hoo Lau, Yuen Len Kong, Tau Wei Phang, Hoon Sin Cheong
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Publication number: 20140230038Abstract: A novel method of dealing with the problem of phishing, pharming, key-logging and man-in-the-middle attacks on internet-based applications which require the application (3) (such as an internet banking website) by the simple transmission of a command via the internet to allow access to the internet-based application (3) whenever the user wishes to access the application, and by transmitting a command via the internet to deny access to the internet-based application at all other times, to present unauthorized access by any unscrupulous parties.Type: ApplicationFiled: February 16, 2012Publication date: August 14, 2014Applicant: E-LOCK CORPORATION SDN. BHD.Inventors: Chik Weng Leong, Chee Ho Lau, Yuen Len Kong, Tau Wei Phang, Hoon Sin Cheong
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Patent number: 7033048Abstract: A height adjusting device for a lamp includes a main body(100) having a motor(120), a casing(160) mounted below the main body(100), an upper terminal unit(200) having upper contact terminals(240) spaced apart from the main body(100) in the casing(160), a moving body(400) moving vertically by a cable(140) connected to the main body(100) and having lower contact terminals(420) corresponding to the terminals(240), and a stopper(300) mounted to the casing(160) to elastically maintain its horizontal state. The moving body(400) has a protrusion(430) at its side to partially contact with the stopper(300) so that the moving body(400) is hooked at a certain height by the stopper(300) when the protrusion(430) ascends over the stopper(300) and then descends, while the moving body(400) may move downward when the side ascends over the stopper(300).Type: GrantFiled: July 14, 2003Date of Patent: April 25, 2006Inventor: Jeong-Hoon Sin