Abstract: Disclosed is a ferroelectric memory device having a memory cell structure where a plurality of ferroelectric capacitor are connected to one switching transistor, and a plurality of data are outputted according to one address input. The ferroelectric memory device comprises a plurality of word lines for driving a corresponding memory cell in accordance with an input address; a plurality of bit lines crossing said word lines, respectively; a plurality of switching transistors connected both to the bit lines and the word lines, respectively; and a plurality of dielectric capacitors wherein one end is coupled in common to a node of the switching transistor, respectively; wherein a plurality of output data are outputted by selecting a memory cell including at least one switching transistor corresponding to the plurality of switching transistors, and to the plurality of dielectric capacitors.

Abstract: A redundancy address bit programming circuit including a redundancy memory cell, includes: program pads for providing signals to first and second program nodes; a ferroelectric capacitor programmed according to a bit value corresponding to a defected address, coupled between the first and second nodes; a load capacitor coupled between the second program node and a ground; a power-up signal generator means for generating a power-up signal to be coupled to the first program node, wherein the power-up signal follows a level of a power signal at a beginning of a power signal supply, and is maintained as a ground level during a stable level state of the power signal supply; a latch means for latching the second program node signal at the beginning of the power signal supply and outputting a latched signal during the stable level state of the power signal supply; and a multiplexer for selectively outputting one of an address bit signal and a reversed address bit signal in response to the latched signal.

Abstract: The present invention provides a reference voltage generating circuit for generating a stable reference voltage and having a long life time, and the reference voltage generating circuit for generating a reference voltage of a ferroelectric memory device having a plurality of bit line pairs, including: a first and second reference word line; a first dummy block comprising a plurality of switching transistors and a plurality of ferroelectric capacitors, wherein gates of the switching transistors are coupled to the first reference word line and drains/sources of the switching transistors are coupled to a bit line of one of the bit line pairs; a second dummy block comprising a plurality of switching transistors and a plurality of ferroelectric capacitors, wherein gates of the switching transistors are coupled to a second reference word line and drains/sources of the switching transistors are coupled to a bit bar line of one of the bit line pairs; and a reference plate line commonly coupled to the ferroelectric ca