Abstract: A semiconductor device includes a substrate including cell and peripheral regions. Landing pads and contact plugs are on the cell and peripheral regions, respectively. A first filler pattern fills regions between the landing pads and between the contact plugs. Outer voids are in the first filler pattern and include first and second outer voids on the cell and peripheral regions, respectively. A second filler pattern covers the first filler pattern and the contact plugs and fills at least a portion of the second outer void. An inner void is in the second outer void and enclosed by the second filler pattern. The first and second filler patterns include the same material. On the cell region, at least a portion of the second filler pattern is located below top surfaces of the landing pads, and a bottom surface of the second filler pattern is partially exposed by the first outer void.

Abstract: An upper electrode of an integrated circuit device includes a metal-containing conductive pattern disposed on a dielectric layer and that fills spaces between a plurality of lower electrodes and covers top surfaces of the plurality of lower electrodes, and a non-metal conductive pattern that includes a bottom surface in contact with a top surface of the metal-containing conductive pattern, and a top surface. The non-metal conductive pattern includes a lower non-metal conductive portion that includes a first top surface at a first height from the bottom surface, and an upper non-metal conductive portion that includes a second top surface at a second height from the bottom surface that is higher than the first height and that protrudes from the first top surface of the lower non-metal conductive portion away from the substrate. A difference between the second height and the first height is greater than the first height.

Abstract: A semiconductor device includes a substrate including cell and peripheral regions. Landing pads and contact plugs are on the cell and peripheral regions, respectively. A first filler pattern fills regions between the landing pads and between the contact plugs. Outer voids are in the first filler pattern and include first and second outer voids on the cell and peripheral regions, respectively. A second filler pattern covers the first filler pattern and the contact plugs and fills at least a portion of the second outer void. An inner void is in the second outer void and enclosed by the second filler pattern. The first and second filler patterns include the same material. On the cell region, at least a portion of the second filler pattern is located below top surfaces of the landing pads, and a bottom surface of the second filler pattern is partially exposed by the first outer void.

Abstract: An upper electrode of an integrated circuit device includes a metal-containing conductive pattern disposed on a dielectric layer and that fills spaces between a plurality of lower electrodes and covers top surfaces of the plurality of lower electrodes, and a non-metal conductive pattern that includes a bottom surface in contact with a top surface of the metal-containing conductive pattern, and a top surface. The non-metal conductive pattern includes a lower non-metal conductive portion that includes a first top surface at a first height from the bottom surface, and an upper non-metal conductive portion that includes a second top surface at a second height from the bottom surface that is higher than the first height and that protrudes from the first top surface of the lower non-metal conductive portion away from the substrate. A difference between the second height and the first height is greater than the first height.

Abstract: A semiconductor device includes a substrate including cell and peripheral regions. Landing pads and contact plugs are on the cell and peripheral regions, respectively. A first filler pattern fills regions between the landing pads and between the contact plugs. Outer voids are in the first filler pattern and include first and second outer voids on the cell and peripheral regions, respectively. A second filler pattern covers the first filler pattern and the contact plugs and fills at least a portion of the second outer void. An inner void is in the second outer void and enclosed by the second filler pattern. The first and second filler patterns include the same material. On the cell region, at least a portion of the second filler pattern is located below top surfaces of the landing pads, and a bottom surface of the second filler pattern is partially exposed by the first outer void.

Abstract: A semiconductor device may include lower electrodes on a substrate, a first upper support layer pattern on upper sidewalls of the lower electrodes, and a dielectric layer and an upper electrode on surfaces of the lower electrodes and the first upper support layer pattern. The lower electrodes may be in a honeycomb pattern with the lower electrodes are at vertexes and center of a hexagon. The first upper support layer pattern may be a first plate shape including openings exposing some of all the lower electrodes. The lower electrodes may form rows in a first direction, the rows arranged in a second direction perpendicular to the first direction. Each opening may expose portions of upper sidewalls of at least four lower electrodes in two adjacent rows. Each of the openings may have a longitudinal direction in the first direction. In semiconductor devices, defects from bending stresses may be decreased.

Abstract: A cache system configured to provide a cache service includes a network switch and a cache device. The network switch is configured to route data associated with a plurality of servers. The cache device is disposed in association with the network switch. The cache device is configured to cache, in at least one memory available to the network switch, data published by the plurality of servers via the network switch. The cache device is also configured to transmit at least some of the cached data in response to a request received from at least one of the plurality of servers. The network switch provides the cache service via the cache device.

Abstract: A cache system configured to provide a cache service includes a network switch and a cache device. The network switch is configured to route data associated with a plurality of servers. The cache device is disposed in association with the network switch. The cache device is configured to cache, in at least one memory available to the network switch, data published by the plurality of servers via the network switch. The cache device is also configured to transmit at least some of the cached data in response to a request received from at least one of the plurality of servers. The network switch provides the cache service via the cache device.