Patents by Inventor Hope Chiu
Hope Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942459Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.Type: GrantFiled: February 14, 2022Date of Patent: March 26, 2024Assignee: Western Digital Technologies, Inc.Inventors: Hua Tan, Hope Chiu, Weiting Jiang, Elley Zhang, Cong Zhang, Simon Dong, Jerry Tang, Rosy Zhao
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Publication number: 20240063092Abstract: A semiconductor device having one or more bifacial semiconductor wafers. The bifacial semiconductor wafer includes a first array of semiconductor dies on a first planar surface and a second array of semiconductor dies on a second planar surface that is opposite the first planar surface. The first array of semiconductor dies are electrically coupled via a first redistribution layer and the second array of semiconductor dies are electrically coupled via a second redistribution layer. One or more through silicon vias electrically couple the first array of semiconductor dies with the second array of semiconductor dies.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Inventors: Sara Shi, Cong Zhang, Hope Chiu
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Publication number: 20230411179Abstract: The present disclosure generally relates to ensuring a plasma plume or cloud that forms during a laser cutting process does not lead to undesired re-deposition of material onto the substrate. At least one electrode is biased to draw the electrons of the plasma plume or cloud towards the electrode and away from the substrate. A vacuum port and/or a blower may be strategically located to ensure proper gas flow away from the substrate and hence, directing of the electrons away from the substrate. In so doing, material re-deposition is less likely to occur.Type: ApplicationFiled: June 10, 2022Publication date: December 21, 2023Applicant: Western Digital Technologies, Inc.Inventors: Cong ZHANG, Hope CHIU, Yiqin HUANG, Guocheng ZHONG, Weiting JIANG, Dongpeng XUE
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Patent number: 11837476Abstract: A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.Type: GrantFiled: May 15, 2020Date of Patent: December 5, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yazhou Zhang, Hope Chiu, Jiandi Du, Paul Qu
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Patent number: 11810896Abstract: A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.Type: GrantFiled: May 18, 2021Date of Patent: November 7, 2023Assignee: Western Digital Technologies, Inc.Inventors: Jiandi Du, Zengyu Zhou, Rui Yuan, Fen Yu, Hope Chiu
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Publication number: 20230299034Abstract: A semiconductor device package includes a semiconductor die including bond pads and an underfill inlet side, a substrate including a first metal layer and lower metal layers underneath the first metal layer, a plurality of metal contacts and trace segment lines disposed in the first metal layer, and a plurality of solder bump rows. Each of the solder bump rows is oriented substantially parallel to the inlet side of the semiconductor die and electrically connects bond pads of the semiconductor die with corresponding metal contacts in the first metal layer of the substrate. Each of the trace segment lines is oriented substantially parallel to the inlet side of the semiconductor die, is electrically coupled to a respective solder bump row of the plurality of solder bump rows, and includes trace segments disposed in the first metal layer and trace segments disposed in one or more of the lower metal layers.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Applicant: Western Digital Technologies, Inc.Inventors: Yihao Chen, Tim Huang, Zengyu Zhou, Rui Yuan, Fen Yu, Hope Chiu
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Publication number: 20230260975Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.Type: ApplicationFiled: February 14, 2022Publication date: August 17, 2023Applicant: Western Digital Technologies, Inc.Inventors: Hua Tan, Hope Chiu, Weiting Jiang, Elley Zhang, Cong Zhang, Simon Dong, Jerry Tang, Rosy Zhao
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Publication number: 20230246000Abstract: A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.Type: ApplicationFiled: February 1, 2022Publication date: August 3, 2023Applicant: Western Digital Technologies, Inc.Inventors: Haiyue Shen, Fen Yu, Hope Chiu, Donghua Wu, Hua Tan, Xinyu Wang, Shenghua Huang
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Publication number: 20230129628Abstract: A semiconductor device package includes a multi-layer substrate including a bottom layer and a top layer. One or more dies are mounted on and electrically coupled to the top layer of the substrate. An electromagnetic interference (EMI) shield encapsulates the substrate and the semiconductor dies. A first plurality of conductive stubs is positioned around edges of the top layer of the substrate. Each of the conductive stubs includes an edge portion having a first thickness and in contact with the EMI shield. A second plurality of conductive stubs is positioned around edges of the bottom layer of the substrate. Each of the second plurality of conductive stubs includes an edge portion having a second thickness less than the first thickness and in contact with the EMI shield.Type: ApplicationFiled: October 25, 2021Publication date: April 27, 2023Applicant: Western Digital Technologies, Inc.Inventors: Simon Dong, Hope Chiu, Weiting Jiang, Elley Zhang, Kent Yang, Hua Tan, Jerry Tang, Rui Guo
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Publication number: 20230102959Abstract: A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in the bond wires electrically connected to the substrate and semiconductor die.Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Applicant: Western Digital Technologies, Inc.Inventors: Hope Chiu, Hua Tan, Kent Yang, Weiting Jiang, Jerry Tang, Simon Dong, Yuequan Shi, Rosy Zhao
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Publication number: 20230011439Abstract: A semiconductor memory device includes first memory dies stacked one upon another and electrically connected one to another by first bond wires, and covered with a first encapsulant. Second memory dies are disposed above the first memory dies, stacked one upon another and electrically connected one to another with second bond wires, and covered with a second encapsulant. A control die may be mounted on the top die in the second die stack. Vertical bond wires extend between the stacked die modules. A redistribution layer is formed over the top die stack and the control die to allow for electrical communication with the memory device. The memory device allows for stacking memory dies in a manner that allows for increased memory capacity without increasing the package form factor.Type: ApplicationFiled: July 7, 2021Publication date: January 12, 2023Applicant: Western Digital Technologies, Inc.Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu
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Publication number: 20220375896Abstract: A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.Type: ApplicationFiled: May 18, 2021Publication date: November 24, 2022Inventors: Jiandi DU, Zengyu ZHOU, Rui YUAN, Fen YU, Hope CHIU
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Patent number: 11508644Abstract: A semiconductor device package includes a substrate, a first heat-generating component positioned on a surface of the substrate, an encapsulant at least partially encapsulating the first heat-generating component, and one or more channels extending through a portion of the encapsulant toward the first heat-generating component. Each of the one or more channels contains a thermally conductive material having a thermal conductivity greater than a thermal conductivity of the encapsulant.Type: GrantFiled: February 26, 2021Date of Patent: November 22, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yazhou Zhang, Shineng Ma, Kent Yang, Hope Chiu
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Patent number: 11488883Abstract: A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.Type: GrantFiled: April 13, 2021Date of Patent: November 1, 2022Assignee: Western Digital Technologies, Inc.Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu, Cong Zhang, Fen Yu, Ada Shen, Gary Zheng, Honny Chen
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Publication number: 20220328374Abstract: A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.Type: ApplicationFiled: April 13, 2021Publication date: October 13, 2022Applicant: Western Digital Technologies, Inc.Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu, Cong Zhang, Fen Yu, Ada Shen, Gary Zheng, Honny Chen
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Publication number: 20220285316Abstract: A memory device includes a substrate, a controller die, a flip chip die, first and second silicon dies, and bond wires. The controller and flip chip dies are attached to the substrate using connection balls and in electrical communication with each other. The first and second silicon dies include respective first and second contact pad surfaces. The bond wires electrically connect the contact pad surfaces to the substrate so the first and second silicon dies communicate with the controller die. The flip chip die and first and second silicon dies are NAND dies, the flip chip die is configured as SLC memory, and the silicon dies are configured as one of MLC memory, TLC memory, or QLC memory.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Inventors: Rui Yuan, Hope Chiu, Paul Qu, Kevin Du, Zengyu Zhou, Yi Su, Shixing Zhu
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Publication number: 20220216128Abstract: A semiconductor device package includes a substrate, a first heat-generating component positioned on a surface of the substrate, an encapsulant at least partially encapsulating the first heat-generating component, and one or more channels extending through a portion of the encapsulant toward the first heat-generating component. Each of the one or more channels contains a thermally conductive material having a thermal conductivity greater than a thermal conductivity of the encapsulant.Type: ApplicationFiled: February 26, 2021Publication date: July 7, 2022Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yazhou Zhang, Shineng Ma, Kent Yang, Hope Chiu
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Publication number: 20220093559Abstract: A packaged semiconductor includes a substrate and a first component disposed on the substrate. The package includes an underfill that is dispensed under and around the first component. The package also includes a second component disposed on the substrate adjacent to the first component that provides a border to the underfill.Type: ApplicationFiled: September 22, 2020Publication date: March 24, 2022Applicant: Western Digital Technologies, Inc.Inventors: Kevin Du, Hope Chiu, Zengyu Zhou, Alex Zhang, Vincent Jiang, Shixing Zhu, Paul Qu, Yi Su, Rui Yuan
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Publication number: 20210335628Abstract: A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.Type: ApplicationFiled: May 15, 2020Publication date: October 28, 2021Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yazhou Zhang, Hope Chiu, Jiandi Du, Paul Qu