Patents by Inventor Horacio Mendez

Horacio Mendez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fully-depleted silicon-on-insulator transistors
    Patent number: 10163934
    Abstract: A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Horacio Mendez
  • FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS
    Publication number: 20180240815
    Abstract: A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 23, 2018
    Inventors: Terence B. HOOK, Horacio MENDEZ
  • Fully-depleted silicon-on-insulator transistors
    Patent number: 9997539
    Abstract: A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Horacio Mendez
  • FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS
    Publication number: 20160372485
    Abstract: A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.
    Type: Application
    Filed: August 30, 2016
    Publication date: December 22, 2016
    Inventors: Terence B. HOOK, Horacio MENDEZ
  • Fully-depleted silicon-on-insulator transistors
    Patent number: 9520329
    Abstract: A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: December 13, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Horacio Mendez
  • Fully-depleted silicon-on-insulator transistors
    Patent number: 9484270
    Abstract: A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: November 1, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Horacio Mendez
  • FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS
    Publication number: 20160079127
    Abstract: A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.
    Type: Application
    Filed: October 14, 2015
    Publication date: March 17, 2016
    Inventors: Terence B. HOOK, Horacio MENDEZ
  • FULLY-DEPLETED SILICON-ON-INSULATOR TRANSISTORS
    Publication number: 20160079277
    Abstract: A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 17, 2016
    Inventors: Terence B. HOOK, Horacio MENDEZ
  • Electrostatic discharge protection device
    Patent number: 5514892
    Abstract: An electrostatic discharge protection device (12) may be fabricated below a wirebond pad (20) to reduce the area impact upon the circuit (10) which incorporates the device. The electrostatic discharge protection device has one or more diodes (13) formed below the wirebond pad. The connections to and from the diodes are by a one or more sets of strips (46). The silicon dioxide formed in the gaps between the strips transfers the downward force exerted during wirebonding to the substrate with causing interlayer delamination.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: May 7, 1996
    Assignee: Motorola, Inc.
    Inventors: Roger Countryman, Gianfranco Gerosa, Horacio Mendez