Patents by Inventor Horia M. Faur

Horia M. Faur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10217893
    Abstract: A method of passivating semiconductor devices using existing tools of junction isolation and phosphosilicate glass (PSG)/borosilicate glass (BSG) etch via room temperature wet chemical growth (RTWCG) processes is provided. Back side processing of the semiconductor device achieves passivation and junction isolation in a single step, while front side processing achieves passivation, PSG/BSG etch, anti-reflection coating and potential induced degradation (PID) mitigation simultaneously. A modified solar cell fabrication method is then provided by integrating the passivation formation method into conventional solar cell manufacturing systems. The resulting solar cells comprise a semiconductor substrate having a front surface and a back surface. The front surface is coated with a SiOx layer less than 50 nm thick, over which a SiNx layer is deposited. On the back surface, another SiOx layer is coated. Experimental data shows high efficiency and mitigated PID of the solar cells.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: February 26, 2019
    Assignee: SPECIAL MATERIALS RESEARCH AND TECHNOLOGY, INC. (SPECMAT)
    Inventors: Gregory C. Knight, Horia M. Faur, Maria Faur
  • Publication number: 20180076341
    Abstract: A semiconductor system includes a silicon substrate and a porous silicon region disposed on the silicon substrate. The porous silicon region is configured to passivate the surface of the silicon substrate via a field effect and to reduce reflection loss on the silicon substrate via an appropriate refractive index. The porous silicon region is manufactured by a stain etching process, which retrofits existing tools for junction isolation and Phosphorus Silicon Glass (PSG) etch in solar cell manufacturing. The retrofitted tools for junction isolation and PSG etch achieves multiple purposes in a single step, including etch-back, PSG etch, antireflection coating, and passivation of the front surface of the solar cell.
    Type: Application
    Filed: March 21, 2016
    Publication date: March 15, 2018
    Inventors: Horia M. Faur, Maria Faur, Gregory C. Knight, Arjun Mendiratta
  • Publication number: 20170098720
    Abstract: This disclosure relates to a Room Temperature Wet Chemical Growth (RTWCG) method and process of SiOX thin film coatings which can be grown on various substrates. The invention further relates to RTWCG method and process suited to grow thin films on the Si substrates used in the manufacture of silicon-based electronic and photonic (optoelectronic) device applications. The invention further relates to processes used to produce SiOX thin film layers for use as passivation layers, low reflectance layers, or high reflectance single layer coatings (SLARC) and selective emitters (SE).
    Type: Application
    Filed: March 18, 2015
    Publication date: April 6, 2017
    Inventors: Horia M. Faur, Maria Faur
  • Publication number: 20160233374
    Abstract: A method of passivating semiconductor devices using existing tools of junction isolation and phosphosilicate glass (PSG)/borosilicate glass (BSG) etch via room temperature wet chemical growth (RTWCG) processes is provided. Back side processing of the semiconductor device achieves passivation and junction isolation in a single step, while front side processing achieves passivation, PSG/BSG etch, anti-reflection coating and potential induced degradation (PID) mitigation simultaneously. A modified solar cell fabrication method is then provided by integrating the passivation formation method into conventional solar cell manufacturing systems. The resulting solar cells comprise a semiconductor substrate having a front surface and a back surface. The front surface is coated with a SiOx layer less than 50 nm thick, over which a SiNx layer is deposited. On the back surface, another SiOx layer is coated. Experimental data shows high efficiency and mitigated PID of the solar cells.
    Type: Application
    Filed: September 16, 2014
    Publication date: August 11, 2016
    Applicant: SPECIAL MATERIALS RESEARCH AND TECHNOLOGY INC (SPECMAT)
    Inventors: Gregory C. KNIGHT, Horia M. FAUR, Maria FAUR
  • Publication number: 20160122554
    Abstract: The present invention relates generally to the field of semiconductors and/or semiconductor structures (e.g., solar cells, etc.), to chemical compositions for manufacturing such semiconductors and/or semiconductor structures, and/or to methods for manufacturing such semiconductors and/or semiconductor structures. In another embodiment, the present invention relates to chemical compositions and methods for controlling surface passivation, dead layer etchback, anti-reflective, potential induced degradation, and other properties of semiconductor surfaces used for various semiconductor applications including, but not limited to, solar cells.
    Type: Application
    Filed: June 10, 2014
    Publication date: May 5, 2016
    Inventors: Horia M. FAUR, Maria FAUR, Mircea FAUR
  • Publication number: 20150376498
    Abstract: This present invention relates to a Room Temperature Wet Chemical Growth (RTWCG) formulations, methods and processes. In one embodiment, the present invention further relates to RTWCG formulations, methods and processes that utilize a low-[HF]. In another embodiment, the present invention relates to RTWCG formulations with improved bath life.
    Type: Application
    Filed: June 30, 2015
    Publication date: December 31, 2015
    Inventors: Horia M. Faur, Maria Faur
  • Patent number: 9068112
    Abstract: Disclosed is a method, process, solar cell design, and fabrication technology for high-efficiency, low-cost, crystalline silicon (Si) solar cells including but not restricted to solar grade single crystal Si (c-Si), multi-crystalline Si (mc-Si), poly-Si, and micro-Si solar cells and solar modules. The RTWCG solar cell fabrication technology creates a RTWCG SiOx thin film antireflection coating (ARC) with a graded index of refraction and a selective emitter (SE). The resulting top surface of the SiOx oxide can be textured (TO) concomitant with the growth process or through an additional mild wet chemical step.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: June 30, 2015
    Assignee: SPECMAT, Inc.
    Inventors: Maria Faur, Horia M. Faur, Mircea Faur
  • Publication number: 20150162460
    Abstract: Disclosed is a method, process, solar cell design, and fabrication technology for high-efficiency, low-cost, crystalline silicon (Si) solar cells including but not restricted to solar grade single crystal Si (c-Si), multi-crystalline Si (mc-Si), poly-Si, and micro-Si solar cells and solar modules. The RTWCG solar cell fabrication technology creates a RTWCG SiOx thin film antireflection coating (ARC) with a graded index of refraction and a selective emitter (SE). The resulting top surface of the SiOx oxide can be textured (TO) concomitant with the growth process or through an additional mild wet chemical step.
    Type: Application
    Filed: November 20, 2014
    Publication date: June 11, 2015
    Inventors: Maria Faur, Horia M. Faur, Mircea Faur
  • Publication number: 20140061531
    Abstract: Disclosed is a method, process, solar cell design, and fabrication technology for high-efficiency, low-cost, crystalline silicon (Si) solar cells including but not restricted to solar grade single crystal Si (c-Si), multi-crystalline Si (mc-Si), poly-Si, and micro-Si solar cells and solar modules. The RTWCG solar cell fabrication technology creates a RTWCG SiOx thin film antireflection coating (ARC) with a graded index of refraction and a selective emitter (SE). The resulting top surface of the SiOx oxide can be textured (TO) concomitant with the growth process or through an additional mild wet chemical step.
    Type: Application
    Filed: March 11, 2011
    Publication date: March 6, 2014
    Inventors: Maria Faur, Horia M. Faur, Mircea Faur
  • Patent number: 6613697
    Abstract: Disclosed is a method for making low metallic impurity SiO-based dielectric thin films on semiconductor substrates using a room temperature wet chemical growth (RTWCG) process for electronic and photonic (optoelectronic) device applications. The process comprises soaking the semiconductor substrate into the growth solution. The process utilizes a mixture of aqueous inorganic or organic based silicon source solution, an inorganic reduction oxidation (redox) aqueous solution, non-invasive inorganic or organic based liquid additives for adjusting the growth rate and reducing the metallic impurity concentration within the SiO-based film, with or without an electron exchange pyridine based component, and an inorganic homogeneous catalyst for enhancing the growth of the SiO-based film.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: September 2, 2003
    Assignee: Special Materials Research and Technology, Inc.
    Inventors: Maria Faur, Horia M. Faur, Mircea Faur
  • Patent number: 6593077
    Abstract: Disclosed is a room temperature wet chemical growth (RTWCG) process of SiO-based insulator coatings on silicon substrates for electronic and photonic (optoelectronic) device applications. The process utilizes a mixture of a silicon source, a pyridinium compound, an aqueous redox solution, and a homogeneous aqueous solution.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: July 15, 2003
    Assignee: Special Materials Research and Technology, Inc.
    Inventors: Maria Faur, Horia M. Faur, Mircea Faur
  • Publication number: 20030027433
    Abstract: Disclosed is a room temperature wet chemical growth (RTWCG) process of SiO-based insulator coatings on silicon substrates for electronic and photonic (optoelectronic) device applications. The process utilizes a mixture of a silicon source, a pyridinium compound, an aqueous redox solution, and a homogeneous aqueous solution.
    Type: Application
    Filed: June 26, 2001
    Publication date: February 6, 2003
    Inventors: Maria Faur, Horia M. Faur, Mircea Faur
  • Patent number: 6409889
    Abstract: This invention refers to a removal and recovery method of pollutant materials. A waste stream source of polluted water and/or waste gases containing waste acids, bases and salts, and/or waste air pollutant suspension particles are fed into a separation reactor. The combined physicochemical effects of removal/recovery of pollutants inside the reactor take place by solubilization, ionization, reaction, deposition and settling, which concurrently remove and separate the pollutants as solid materials, deposited on selective electrodes sets, as gases and as sludge and/or precipitates. The reactor is kept at the working temperature using a waste industrial heat, and the separation processes take place by applying a voltage source between a spaced apart system of selective electrodes, and by using a ionizing source of waste spent fuel nuclear bars or electromagnetic radiation.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: June 25, 2002
    Assignee: Special Materials Research and Technology, Inc.
    Inventors: Mircea Faur, Maria Faur, Horia M. Faur
  • Patent number: 6080683
    Abstract: Disclosed is a room temperature wet chemical growth (RTWCG) process of SiO-based insulator coatings on silicon substrates for electronic and photonic (optoelectronic) device applications. The process includes soaking the Si substrates into the growth solution. The process utilizes a mixture of H.sub.2 SiF.sub.6, N-n-butylpyridinium chloride, redox Fe.sup.2+ /Fe.sup.3+ aqueous solutions, and a homogeneous catalyst.
    Type: Grant
    Filed: March 22, 1999
    Date of Patent: June 27, 2000
    Assignee: Special Materials Research and Technology, Inc.
    Inventors: Maria Faur, Mircea Faur, Dennis J. Flood, Sheila G. Bailey, Horia M. Faur