Abstract: Disclosed is a system comprising a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying a group of memory cells corresponding to a first range of logical block addresses (LBAs). The operations performed by the processing device further include receiving a memory access command with respect to the group of memory cells. The operations performed by the processing device further include responsive to determining that a data structure associated with the group of memory cells references a second range of LBAs, blocking the memory access command; responsive to determining that the first range of LBAs does not include each LBA of the second range of LBAs, performing, on the group of memory cells, a trim operation; and responsive to determining that the data structure indicates the completion of the trim operation, performing a memory access operation specified by the memory access command.

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include receiving, by the processing device, a trim command on the memory device, wherein the trim command references a range of logical block addresses (LBAs). The operations performed by the processing device further include identifying a group of memory cells corresponding to the range of LBAs, wherein the group of memory cells comprises one or more management units (MUs). The operations performed by the processing device further include updating a data structure associated with the group of memory cells to reference the request; receiving a memory access command with respect to the group of memory cells.

Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include receiving, by the processing device, a trim command on the memory device, wherein the trim command references a range of logical block addresses (LBAs). The operations performed by the processing device further include identifying a group of memory cells corresponding to the range of LBAs, wherein the group of memory cells comprises one or more management units (MUs). The operations performed by the processing device further include updating a data structure associated with the group of memory cells to reference the request; receiving a memory access command with respect to the group of memory cells.

Abstract: A system and method for efficient cache flushing are provided. The disclosed method includes maintaining a data structure in connection with a plurality of blocks used for data caching, the data structure including a row lock wait list section. The method further includes receiving an Input/Output (I/O) request, performing a hash search for the I/O request against the data structure, and based on the results of the hash search, locking at least one row in a data cache thereby preventing read and write operations from being performed on the at least one row until the at least one row is unlocked.

Abstract: A system and method for efficient write through processing of Input/Output (I/O) requests are provided. One example of the illustrative method includes receiving a first write request to a first row, while processing the first write request, receiving a subsequent write request to the first row, and then caching the subsequent write request for processing until the first write request is completed.

Abstract: A system and method for managing bad blocks in a hardware accelerated caching solution are provided. The disclosed method includes receiving an Input/Output (I/O) request, performing a hash search for the I/O request against a hash slot data structure, and based on the results of the hash search, either performing the I/O request with a data block identified in the I/O request or diverting the I/O request to a new data block not identified in the I/O request. The diversion may also include diverting the I/O request from hardware to firmware of a memory controller.

Abstract: A system and method for efficient cache flushing are provided. The disclosed method includes maintaining a data structure in connection with a plurality of blocks used for data caching, the data structure including a row lock wait list section. The method further includes receiving an Input/Output (I/O) request, performing a hash search for the I/O request against the data structure, and based on the results of the hash search, locking at least one row in a data cache thereby preventing read and write operations from being performed on the at least one row until the at least one row is unlocked.

Abstract: A method for managing a pool buffers includes establishing a first buffer class with a first allowable number of buffers, and a first reserved number of buffers that are reserved for the first buffer class in the pool of buffers even if no Input/Output (I/O) operation is running in connection with the first buffer class. The method includes establishing a second buffer class with a second allowable number of buffers, and a second reserved number of buffers that are reserved for the second buffer class in the pool of buffers even if no I/O operation is running in connection with the second buffer class. The first buffer is enabled class to have more than the first allowable number of buffers as long as a number of buffers allocated to the second buffer class is fewer than the second allowable number of buffers.

Abstract: A system and method for performing a copyback operation are provided. The disclosed method includes initiating a copyback process to move data from an online data storage drive to a spare data storage drive by setting an indicator in hardware to divert all write completions on the online data storage drive. The method further includes, while the indicator in hardware is set to divert the write completions, incrementing on a per-strip basis a copy of data from the online data storage drive to the spare data storage drive. The method further includes only after all data from the online data storage drive has been copied to the spare data storage drive, changing the setting of the indicator in hardware so that write requests received for the online data storage drive during the copyback process are re-issued on to the spare data storage drive.

Abstract: A system and method for efficient cache flushing are provided. The disclosed method includes allocating one or more Internal Scatter Gather Lists (ISGLs) for the cache flush, populating the one or more ISGLs with Cache Segment Identifiers (CSIDs) and corresponding Buffer Segment Identifiers (BSIDs) of each strip that is identified as dirty, of a skip-type Internal Scatter Gather Element (ISGE), or of a missing arm-type ISGE. The disclosed method further includes allocating a flush Local Message Identifier (LMID) as a message to be used in connection with processing the cache flush, populating the flush LMID with an identifier of the one or more ISGLs, and transferring the flush LMID to a cache manager module to enable the cache manager module to execute the cache flush based on information contained in the flush LMID.

Abstract: A system and method for efficient cache buffering are provided. The disclosed method determining that a read-ahead operation is to be performed in response to receiving a host Input/Output (I/O) command. In response to determining that the read-ahead operation is to be performed, allocating a new Local Message Identifier (LMID) for the read-ahead operation. The method further includes sending a buffer allocation request to a buffer manager module, the buffer allocation request containing parameters associated with the read-ahead operation and then causing the buffer manager module to allocate at least one Internal Scatter Gather List (ISGL) and Buffer Section Identifier (BSID) in accordance with the parameters contained in the buffer allocation request. The method further includes enabling the cache manager module to perform a hash search using a row or strip number and identification information available in the new LMID.

Abstract: A system and method for efficient cache buffering are provided. The disclosed method includes receiving an Input/Output (I/O) command from a host system at a storage controller, parsing the I/O command at the storage controller with a host I/O manager to extract command instructions therefrom. The host I/O manager is able to generate at least one local message that includes the command instructions extracted from the I/O command and transmit the at least one local message to a cache manager. The cache manager is enabled to work in local memory to execute the command instructions contained in the at least one message. The cache manager is also configured to chain multiple buffer segments together on-demand to support multiple stripe sizes that are specific to the I/O command received from the host system.

Abstract: A system and method for efficient cache flushing are provided. The disclosed method includes allocating one or more Internal Scatter Gather Lists (ISGLs) for the cache flush, populating the one or more ISGLs with Cache Segment Identifiers (CSIDs) and corresponding Buffer Segment Identifiers (BSIDs) of each strip that is identified as dirty, of a skip-type Internal Scatter Gather Element (ISGE), or of a missing arm-type ISGE. The disclosed method further includes allocating a flush Local Message Identifier (LMID) as a message to be used in connection with processing the cache flush, populating the flush LMID with an identifier of the one or more ISGLs, and transferring the flush LMID to a cache manager module to enable the cache manager module to execute the cache flush based on information contained in the flush LMID.

Abstract: A system and method for managing bad blocks in a hardware accelerated caching solution are provided. The disclosed method includes receiving an Input/Output (I/O) request, performing a hash search for the I/O request against a hash slot data structure, and based on the results of the hash search, either performing the I/O request with a data block identified in the I/O request or diverting the I/O request to a new data block not identified in the I/O request. The diversion may also include diverting the I/O request from hardware to firmware of a memory controller.

Abstract: A method for managing a pool buffers includes establishing a first buffer class with a first maximum allowable number of buffers, and a first reserved number of buffers that are reserved for the first buffer class in the pool of buffers even if no Input/Output (I/O) operation is running in connection with the first buffer class. The method includes establishing a second buffer class with a second maximum allowable number of buffers, and a second reserved number of buffers that are reserved for the second buffer class in the pool of buffers even if no I/O operation is running in connection with the second buffer class. The first buffer is enabled class to have more than the first maximum allowable number of buffers as long as a number of buffers allocated to the second buffer class is fewer than the second maximum allowable number of buffers.

Abstract: A system and method for efficient cache buffering are provided. The disclosed method determining that a read-ahead operation is to be performed in response to receiving a host Input/Output (I/O) command. In response to determining that the read-ahead operation is to be performed, allocating a new Local Message Identifier (LMID) for the read-ahead operation. The method further includes sending a buffer allocation request to a buffer manager module, the buffer allocation request containing parameters associated with the read-ahead operation and then causing the buffer manager module to allocate at least one Internal Scatter Gather List (ISGL) and Buffer Section Identifier (BSID) in accordance with the parameters contained in the buffer allocation request. The method further includes enabling the cache manager module to perform a hash search using a row or strip number and identification information available in the new LMID.

Abstract: A system and method for performing a copyback operation are provided. The disclosed method includes initiating a copyback process to move data from an online data storage drive to a spare data storage drive by setting an indicator in hardware to divert all write completions on the online data storage drive. The method further includes, while the indicator in hardware is set to divert the write completions, incrementing on a per-strip basis a copy of data from the online data storage drive to the spare data storage drive. The method further includes only after all data from the online data storage drive has been copied to the spare data storage drive, changing the setting of the indicator in hardware so that write requests received for the online data storage drive during the copyback process are re-issued on to the spare data storage drive.

Abstract: A system and method for efficient cache buffering are provided. The disclosed method includes receiving a host command from a host, extracting command information from the host command, determining an Input/Output (I/O) action to be taken in connection with the host command, determining that the I/O action spans more than one strip, and based on the I/O action spanning more than one strip, allocating a cache frame anchor for a row on-demand along with a cache frame anchor for a strip to accommodate the I/O action.

Abstract: A system and method for efficient cache buffering are provided. The disclosed method includes receiving a host command from a host, extracting command information from the host command, determining an Input/Output (I/O) action to be taken in connection with the host command, identifying a particular memory module from among a plurality of memory modules to execute the I/O action, generating an accelerated I/O message for transmission to the particular memory module, the accelerated I/O message comprising at least one Internal Scatter Gather List (ISGL) having a plurality of Scatter Gather Extents (SGEs) that enable the particular memory module to execute the I/O action solely based on the at least one ISGL, and transmitting the accelerated I/O message to the particular memory module.

Abstract: An apparatus having a cache and a circuit is disclosed. The cache includes a plurality of cache lines. The cache is configured to (i) store a plurality of data items in the cache lines and (ii) generate a map that indicates a dirty state or a clean state of each of the cache lines. The cache also has a write-back policy to a memory. The circuit is configured to (i) check a location in the map corresponding to a read address of a read request and (ii) obtain read data directly from the memory by bypassing the cache in response to the location having the clean state.