Patents by Inventor Horia Toma

Horia Toma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness
    Patent number: 9990453
    Abstract: Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: June 5, 2018
    Assignee: SYNOPSYS, INC.
    Inventors: Namit K. Gupta, Jean-Marc A. Forey, Mahantesh D. Narwade, Horia A. Toma
  • CLOCK-DOMAIN-CROSSING SPECIFIC DESIGN MUTATIONS TO MODEL SILICON BEHAVIOR AND MEASURE VERIFICATION ROBUSTNESS
    Publication number: 20160292331
    Abstract: Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 6, 2016
    Applicant: SYNOPSYS, INC.
    Inventors: Namit K. Gupta, Jean-Marc A. Forey, Mahantesh D. Narwade, Horia A. Toma
  • Dynamic FIFO for simulation
    Patent number: 7346483
    Abstract: To perform a simulation, a design can be divided into “blocks” described by models. To ensure that data is efficiently transferred from an source model to a destination model, a dynamic first-in first-out (FIFO) can be placed between these models. The initial size of the dynamic FIFO can be set to a relatively small value. To prevent deadlock, the size of the FIFO can be automatically increased in size by increments. In this manner, the memory resources of the FIFO can be tightly controlled. Advantageously, the size of the optimized dynamic FIFO can be used as the desired size of the FIFO implemented in silicon, thereby also ensuring efficient use of silicon resources.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: March 18, 2008
    Assignee: Synopsys, Inc.
    Inventors: Horia Toma, Thorsten Heiner Groetker, Srinivas Bongoni, Andrea Kroll
  • Dynamic FIFO for simulation
    Publication number: 20050080610
    Abstract: To perform a simulation, a design can be divided into “blocks” described by models. To ensure that data is efficiently transferred from an source model to a destination model, a dynamic first-in first-out (FIFO) can be placed between these models. The initial size of the dynamic FIFO can be set to a relatively small value. To prevent deadlock, the size of the FIFO can be automatically increased in size by increments. In this manner, the memory resources of the FIFO can be tightly controlled. Advantageously, the size of the optimized dynamic FIFO can be used as the desired size of the FIFO implemented in silicon, thereby also ensuring efficient use of silicon resources.
    Type: Application
    Filed: October 10, 2003
    Publication date: April 14, 2005
    Inventors: Horia Toma, Thorsten Groetker, Srinivas Bongoni, Andrea Kroll