Patents by Inventor Hormazdyar M. Dalal
Hormazdyar M. Dalal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8536685Abstract: In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer.Type: GrantFiled: January 24, 2012Date of Patent: September 17, 2013Assignee: Semiconductor Components Industries, LLCInventors: Hormazdyar M. Dalal, Jagdish Prasad
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Publication number: 20120119340Abstract: In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer.Type: ApplicationFiled: January 24, 2012Publication date: May 17, 2012Inventors: Hormazdyar M. Dalal, Jagdish Prasad
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Patent number: 8129266Abstract: In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer.Type: GrantFiled: July 9, 2008Date of Patent: March 6, 2012Assignee: Semiconductor Componenets Industries, LLCInventors: Hormazdyar M. Dalal, Jagdish Prasad
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Publication number: 20100006989Abstract: In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer.Type: ApplicationFiled: July 9, 2008Publication date: January 14, 2010Inventors: Hormazdyar M. Dalal, Jagdish Prasad
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Patent number: 6972209Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: GrantFiled: November 27, 2002Date of Patent: December 6, 2005Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engle, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw
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Publication number: 20040101663Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: ApplicationFiled: November 27, 2002Publication date: May 27, 2004Inventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engel, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw
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Patent number: 6618267Abstract: A multi-level package, and method for making same, that offers a small size with compartmentalized areas that allow for radiation shielding is disclosed. In its simplest embodiment, the invention comprises two cards and an interposer interposed between the two cards. The interposer preferably has an opening, and the combination of the interposer's opening and the two cards form a cavity. The cavity allows for a high amount of components to be packed into a small, three-dimensional space. The interposer supports can act like a Faraday shield. The two cards and interposer can be multi-layered and support any type of chip or package connection on each side of each card or interposer, including through-hole, surface mount, and direct-chip attachment connections. Finally, pick-up plates or heat sinks can be attached to the package.Type: GrantFiled: September 22, 1998Date of Patent: September 9, 2003Assignee: International Business Machines CorporationInventors: Hormazdyar M. Dalal, Gene Joseph Gaudenzi
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Patent number: 6348731Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with hafnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper interstitial positions.Type: GrantFiled: January 29, 1999Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Leon Ashley, Hormazdyar M. Dalal, Du Binh Nguyen, Hazara S. Rathore, Richard G. Smith
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Patent number: 6336262Abstract: A capacitor having a multilevel interconnection technology and process thereof. Also disclosed is a process of electrically connecting a capacitor to an object, comprising the steps of first obtaining a capacitor. At least one solder ball is reflowed and secured onto the capacitor. The solder ball is in electrical communication with the capacitor through a contacting means. On this reflowed solder ball a cap of low melting point metal is secured. This can be done in a number of ways. The preferred way is to positioning a mask over the solder ball such that a portion of the solder ball is exposed through openings in the mask. At least one layer of a low melting point metal is deposited on the exposed surface of the solder ball through the mask, and thereby forming a capacitor with a multilevel interconnect cap. The low melting point metal can interact with the surface of the solder ball to form a cap of an eutectic or a liquefied portion. The cap portion can then be joined to the object.Type: GrantFiled: April 30, 1997Date of Patent: January 8, 2002Assignee: International Business Machines CorporationInventors: Hormazdyar M. Dalal, Gene Joseph Gaudenzi, Rebecca Y. Gorrell, Mark A. Takacs, Kenneth J. Travis, Jr.
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Patent number: 6323554Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH4 to WF6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten.Type: GrantFiled: July 10, 1998Date of Patent: November 27, 2001Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Jerome J. Cuomo, Hormazdyar M. Dalal, Louis L. Hsu
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Patent number: 6294835Abstract: The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.Type: GrantFiled: August 2, 1999Date of Patent: September 25, 2001Assignee: International Business Machines CorporationInventors: Hormazdyar M. Dalal, Du Binh Nguyen, Hazara S. Rathore
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Patent number: 6287954Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with hafnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper interstitial positions.Type: GrantFiled: December 9, 1999Date of Patent: September 11, 2001Assignee: International Business Machines CorporationInventors: Leon Ashley, Hormazdyar M. Dalal, Du Binh Nguyen, Hazara S. Rathore, Richard G. Smith
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Publication number: 20010013423Abstract: A structure and method is disclosed for directly attaching a device or package on flexible organic circuit carriers having low cost and high reliability.Type: ApplicationFiled: September 18, 1997Publication date: August 16, 2001Inventors: HORMAZDYAR M. DALAL, KENNETH M. FALLON, GENE J. GAUDENZI, CYNTHIA S. MILKOVICH
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Patent number: 6258710Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.Type: GrantFiled: December 10, 1999Date of Patent: July 10, 2001Assignee: International Business Machines CorporationInventors: Hazara S. Rathore, Hormazdyar M. Dalal, Paul S. McLaughlin, Du B. Nguyen, Richard G. Smith, Alexander J. Swinton, Richard A. Wachnik
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Patent number: 6147402Abstract: Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten.Type: GrantFiled: July 10, 1998Date of Patent: November 14, 2000Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Jerome J. Cuomo, Hormazdyar M. Dalal, Louis L. Hsu
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Patent number: 6133139Abstract: The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.Type: GrantFiled: October 8, 1997Date of Patent: October 17, 2000Assignee: International Business Machines CorporationInventors: Hormazdyar M. Dalal, Du Binh Nguyen, Hazara S. Rathore
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Patent number: 6130161Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with halfnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper intersititial positions.Type: GrantFiled: May 30, 1997Date of Patent: October 10, 2000Assignee: International Business Machines CorporationInventors: Leon Ashley, Hormazdyar M. Dalal, Du Binh Nguyen, Hazara S. Rathore, Richard G. Smith
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Patent number: 6069068Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.Type: GrantFiled: October 8, 1997Date of Patent: May 30, 2000Assignee: International Business Machines CorporationInventors: Hazara S. Rathore, Hormazdyar M. Dalal, Paul S. McLaughlin, Du B. Nguyen, Richard G. Smith, Alexander J. Swinton, Richard A. Wachnik
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Patent number: 6033939Abstract: A method is provided for the fabrication of fuses within a semiconductor IC structure, which fuses are delectable by a laser pulse or a low voltage electrical pulse typically below 3.5 V to reroute the electrical circuitry of the structure to remove a faulty element. The fuses are formed on the surface of circuitry which is coplanar with a surrounding dielectric such as the circuitry formed by a Damascene method. A preferred fuse material is silicon-chrome-oxygen and the preferred circuitry is copper.Type: GrantFiled: April 21, 1998Date of Patent: March 7, 2000Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Hormazdyar M. Dalal, Du B. Nguyen, Hazara S. Rathore
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Patent number: 5981374Abstract: The present invention relates to the field of semiconductor manufacturing, and more specifically to methods of forming sub-half-micron multi-level interconnect structures for integrated circuits. The inventive structure and process are spike free and that has resulted in improved circuit performance, reliability and process yields. The inventive structure and process have a plurality of insulator layers where each of the adjoining insulator layers are of a different material.Type: GrantFiled: April 29, 1997Date of Patent: November 9, 1999Assignee: International Business Machines CorporationInventors: Hormazdyar M. Dalal, Du Binh Nguyen, Hazara S. Rathore